Accelerating Custom IC Implementation: Speed without compromise
This video demonstrates how
IC Station’s tight integration to schematic capture and Calibre verification can help you create analog, mixed-signal, and custom digital IC layouts that are finely tuned to meet strict constraints on performance, area, power, manufacturability, and yield.
Traditionally, designers used custom layout techniques to maximize their flexibility, but they also prolonged layout times often into the critical path of a tapeout. To further complicate matters, design rules are increasing in number and complexity, which causes longer verification cycles. And SoCs are only getting larger while project schedules shrink, requiring parallel circuit and layout design across globally dispersed teams.
These challenges demand better methodologies that can significantly accelerate layout productivity without compromising quality and flexibility.
What You Will Learn
- Schematic-driven layout
- Interactive custom routing
- High speed automatic routing
- Physical verification
- Parasitic extraction and back-annotation
- Post-layout simulation and analysis
- IC Station
- IC Station SDL
- Design Architect IC
Technical Marketing Engineer
Mentor Graphics Corp.
- IC Station SDL
- Parameterized layout device generation based on the source schematic
- Devices and pin placement and optimization
- ICassemble IRoute
- Connectivity-based interactive routing
- On-the-fly DRC-aware routing
- Pushing and sliding of routes
- ICassemble ARoute
- High speed, connectivity-based DRC-aware auto routing
- Constraint-driven, net-class-based routing
- Calibre Verification
- Inline DRC for full/area-based DRC checking, integrated nto layout window
- Inline LVS run and debugging integrated into layout window
- Calibre xRC parasitic DSPF netlist extraction with schematic-based names and hierarchy
- Eldo for post-layout simulation
- Design Architect-IC, IC Station and Calibre RVE for post-layout parasitic analysis