Signoff Physical Verification in the Place and Route Flow
This presentation delves into the sources of manufacturing variability, their effect on the traditional design and verification flows, and the emerging EDA solutions that fully integrate the design and physical signoff tasks.
The newest bottleneck in physical design and verification is meeting all the design rules checking (DRC) and design for manufacturing (DFM) closure constraints. Once post-processing steps, layout engineers are increasingly being asked to consider the effects of increased manufacturing variability. This change in layout restrictions calls for supporting changes in the EDA tool flow. File-based iterations between physical signoff tools, to detect violations, and implementation tools, to fix them, are increasingly untenable.
True DRC/DFM signoff must be fully integrated into the place and route environment so all the design objectives—performance, power, area, manufacturability—can be addressed concurrently in the full context of the design. This allows for tighter design margins and eliminates late-stage surprises in the design flow.
What You Will Learn
- Limitations of the Place and Route DRC verification engines
- Benefits of Physical Verification Signoff in Place and Route environment
About the Presenter
Clément is currently a Technical Marketing Engineer for the Calibre LFD and inRoute products, helping customers implement lithography analysis tools for their designers. His responsibilities also include providing support to teams implementing inRoute in their Place & Route flows.
He started at Mentor Graphics as a European Product Specialist for the Calibre OPC products, providing pre- and post- sales support to clients in Europe. Prior to joining Mentor Graphics, he worked as an engineer at the Advanced Mask Technology Center in Dresden.
Clément holds an MSc in Microelectronics from the ESIEE Paris Engineering school.
Who Should View
- Physical Design Team Manager
- Place and Route Engineer
- CAD Manager/Engineer