Finding and Fixing Double Patterning Errors in 20nm Design
On-demand Web Seminar
Winner of the Customer's Choice award at TSMC's Open Innovation Platform Ecosystem event in San Jose, CA, this presentation describes the new constraints that double patterning brings to the 20nm node, and how IC designers can deal with DP related design rule violations.
Double patterning brings a new set of design constraints to the 20nm node and it has caused designers to get very concerned about how they find and deal with DP related violations. In this presentation, we will explain the kinds of violations that are unique to double patterning design and how the jointly developed tools with Mentor and TSMC help identify them and aide the designer in fixing them. Examples and best practices methods will also be discussed.
What You Will Learn
- A basic introduction to double patterning rules and violations
- Example challenges with DP error debug
- Recommended techniques for best fixing DP violations
- How to use Mentor's DP fixing hints to improve debug efficiency
About the Presenter
David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics in Wilsonville, Oregon. For the last four years at Mentor he has been driving the roadmap for developing EDA tools to solve the growing issues in design to process interactions (DFM) that are creating ever increasing yield problems in advanced semiconductor manufacturing. Previously, he has 15 years of experience driving yield enhancement programs in Semiconductor manufacturing at LSI Logic, Motorola, Harris and General Electric. He has also led software development teams in delivering yield enhancement and data mining solutions to semiconductor manufacturing. He is extensively published in papers and patents on semiconductor processing and yield enhancement. He received his BSEE from Clemson University in 1987 and his MSEE from North Carolina State University in 1988.
This presentation was co-authored with Chin-Chang (Peter) HSU who is a principal engineer at TSMC, Design Methodology Division.
Who Should View
- CAD managers and engineers supporting design teams using TSMC N20 process
- Design managers and engineers using TSMC N20 process