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Freescale Harnesses the Power of eqDRC to Address Recommended Rules



Recommended rules attempt to capture layout configurations that can interact with manufacturing variation to cause statistical yield loss in production. Although, stated as “rules” the sensitivities are not black and white but statistical functions. The number of violations that recommended rule checks generate can make it difficult to define appropriate expectations for how many to fix and which ones should be fixed. Finally, when trying to fix these violations it is easy to create a worse violation in the process making optimization difficult.

Robert Boone at Freescale in Austin, TX will show how their DFM team has used the capabilities of eqDRC in Calibre nmDRC to implement more effective approaches to scoring and prioritizing recommended rules. In addition, they have built functionality to assess the trade-offs in potential fixes to identify low hanging fruit for the designer. By setting targets for the design teams to fix most of these low hanging opportunities they have been able to improve the potential yield of their designs.

What You Will Learn

  • How Freescale is leveraging the capabilities of eqDRC to address recommended rules
  • How Freescale has implemented DFM scoring of recommended rules for prioritization of manufacturing issues
  • How Freescale calculates potential fixes (improvability) for recommended rule violations and addresses trade-offs between rules when trying to calculate a fix
  • How Freescale has improved their design yields using this scoring and improvability methodology


About the Presenters

Presenter Image David Abercrombie

David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics in Wilsonville, Oregon. For the last four years at Mentor he has been driving the roadmap for developing EDA tools to solve the growing issues in design to process interactions (DFM) that are creating ever increasing yield problems in advanced semiconductor manufacturing. Previously, he has 15 years of experience driving yield enhancement programs in Semiconductor manufacturing at LSI Logic, Motorola, Harris and General Electric. He has also led software development teams in delivering yield enhancement and data mining solutions to semiconductor manufacturing. He is extensively published in papers and patents on semiconductor processing and yield enhancement. He received his BSEE from Clemson University in 1987 and his MSEE from North Carolina State University in 1988.

Presenter Image Robert Boone

Robert has been working in the fields of computational geometry and software development for the last eighteen years. He holds a B.S. in Mathematics from the University of Texas at San Antonio, an M.A. in Germanic Languages from the University of Texas at Austin and an M.E. from the University of Colorado at Boulder. After seven years working in artificial intelligence for the defense industry, Robert joined the OPC team at Motorola (now Freescale), working for five years in Austin before taking a four-year assignment in France to work for the company in the Crolles2 partnership. Robert joined the Crolles2 DFM team in 2006 and returned to Austin in 2007, where he leads Freescale’s IP DFM team.

Who Should View

  • Design Engineers wanting to learn better ways to address recommended rules
  • CAD Engineers trying to develop improved decks for DFM analysis and optimization
  • Process development engineers trying to provide better guidance to designers for improving layout robustness to manufacturing variability

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