Why IC Designers Need New Double Patterning Debug Capabilities at 20nm
/mentor2/images/player.swf
540
960
uuid=78c2a2b6-006d-41ae-9ef4-697e2b72202e&ischaptered=false&mgcbitrate=mgcvbitrate&id=flashreplace&image=/products/ic_nanometer_design/multimedia/double-patterning-at-20nm/multimedia_image/ic-tsmc-brunet-interview.jpg&file=mp4s/ic-tsmc-brunet-interview.mp4&streamer=rtmp%3A//mgraphics.fcod.llnwd.net/a3661/o33&autostart=false&skin=/mentor2/images/bright.swf
Description
Jean-Marie Brunet, Director of DFM Product Marketing, discusses Mentor's history of collaboration with TSMC and highlights their work on design enabling support for 20nm.
Details
Design Areas IC Design
Design Tasks Calibre Interfaces