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How Physical Implementation realizes Power Intent

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Overview

During is session we will discuss how to handle power intent within a Place and Route environment whilst meeting all design constraints, modes and corners for best QoR.

The Place and Route stage of a design flow is where the power intent is realized physically for the first time. Power domains become real areas on silicon, interconnect created for power routes, power switches arrayed & placed etc.

Time and effort spent defining power intent and architecting the design earlier in the design flow pays off by giving the digital layout engineer a clear and efficient path to completing the design physically.

For each power state, the operating conditions and functional mode (i.e. sleep, standby, low power, high performance etc) will require appropriate libraries and timing constraints. The power state requirements will also drive the insertion of level-shifters, isolation and retention cells.

What You Will Learn

  • What power intent information is required before physical implementation of a Low Power design
  • How to interpret power intent physically
  • The use of a “power format” file which defines the power state table for a design.
  • Features to look for with in a Place and Route tool for low power design

About the Presenter

Presenter Image Tony Newbold

Tony Newbold Joined Mentor in May 2009. Previously he worked for Synopsys and Avanti as an application consultant for 9 years where he worked with all the Place and route tools such as Apollo, Astro, PhC and ICC as well as being the European Product Lead for floorplanning products. Before Synospsys/Avanti, Tony spent 3 & a half years working for Atmel doing digital layout.

Who Should View

  • IC designers
  • Digital layout designers
 
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