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Robust Verification of Low Power Designs

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Overview

The increased use of thin-oxide transistors, which are less robust to electrical failure in mixed-signal and multi-voltage designs, have ushered in a new ear of verification challenges. Correct connection of these devices to the appropriate voltage domains are a critical factor when long-term circuit reliability is required. Preventing electrical failure means IC designers should utilize new techniques to validate ESD structures for circuits that cross multiple power domains, particularly those with sensitive analog circuits. This session describes these challenges and how Calibre PERC can provide a comprehensive platform to identify and address these problems.

What You Will Learn

  • How to readily identify devices that cross multiple power domains
  • Verification techniques to ensure that your devices are not exposed to electrical overstress (EOS) or electrostatic discharge (ESD) vulnerabilities
  • Techniques for automating the detection of undesirable circuit configurations that impact design performance and reliability

About the Presenter

Presenter Image Matthew Hogan

Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is an IEEE Senior member and ACM member and holds a Bachelor of Engineering from the Royal Melbourne Institute of Technology and an MBA from Marylhurst University. He is actively working with customers who have an interest in Calibre PERC. He can be reached at matthew_hogan@mentor.com.

Who Should View

  • Digital designers
  • SoC designers
  • Design Engineers and managers with multi-power domains
  • Circuit designers
  • Physical Verification specialists

Products Covered

 
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