Overcoming Complexity in the Physical Verification Signoff Process
As we progress to ever smaller nodes, the number of rule checks keeps growing along with the complexity of the rules. Custom and AMS designers are experiencing more and more iterations, slowing down the convergence to final signoff.
Design rules are now so complex that fixing one problem creates another, but designers don’t know that until they run a full DRC verification. After iteration, designers find out they can’t make fixes because they don’t have the area to do so; they’ve boxed themselves in with a particular configuration.
Calibre RealTime is a new product which runs sign-off Calibre DRC checking in the design environment as the designers edit their design.
What You Will Learn
- The architecture for advanced verification. Physical Verification trends and continuously increasing DRC complexity.
- Different kinds of DRC checks and methodologies that are required for advanced process nodes.
- Calibre Real Time - The dynamic application of signoff-quality DRC during layout creation, enabling quick, accurate error correction against the full range of up-to-date, foundry-qualified design rules.
About the Presenter
Arvind Bashyam is holding a Bachelor of Engineering, a Master of Research and a Master of Science and graduated at the Napier University (UK) in 2006.
After having previously worked for Firstco and Axell Wireless Arvind joined Mentor Graphics in 2009 as a European Application Engineer supporting customers across Europe on IC physical verification projects.
Who Should View
- Engineers and engineering managers currently doing Custom/Analog Mixed-Signal design and working on advanced process nodes.