IC Nanometer Design News & Industry Articles
Press Releases
- SMIC Employs Mentor Graphics Calibre PERC for Reliability Verification of Multi-Power Domain SoCs (May 22, 2012)
- GLOBALFOUNDRIES Improves IC Reliability with Customized Circuit Checks Using Mentor Graphics Calibre PERC (May 22, 2012)
- Calibre Flow Developed with Mentor Graphics Consulting Boosts GLOBALFOUNDRIES Silicon Yield (Mar 8, 2012)
- Samsung DFM Ready for 20 nm Based on Mentor Graphics Calibre Platform (Mar 1, 2012)
- Fujitsu Semiconductor Expands Use of Calibre for Advanced IC Physical Verification and Design for Manufacturing (Jan 23, 2012)
- Mentor Graphics Receives TSMC’s Partner of the Year Award for 3D-IC Design Enablement (Nov 11, 2011)
- Mentor Graphics Announces Completion of 20 nm Test Chip Tapeout with STMicroelectronics Using Olympus-SoC Place and Route System (Nov 4, 2011)
- Mentor Graphics and TSMC Address Advanced Node Fill Requirements Using Calibre SmartFill (Sep 14, 2011)
Press Release Archives
Industry Articles
- A Quadrant-XYZ Routing Algorithm for 3-D Asymmetric Torus Network-on-Chip (Oct 30, 2011)
- Circuit Simulation and IC Layout update from Mentor at DAC (Jun 17, 2011)
- Evolution of manufacturing closure for advanced nodes (Part 2) (Feb 18, 2011)
- Whither interoperability: The myth of the grand, unifying EDA database (Dec 6, 2010)
- New IC verification techniques for analog content (Nov 17, 2010)
- Seven Essential Principles of Analog BIST (Nov 4, 2010)
- 22nm-node logic lithography at the boundary of the resolution limit (Nov 3, 2010)
- The Future of IC Design Verification (Nov 1, 2010)
- Evolution of manufacturing closure for advanced nodes (Part 1) (Sep 20, 2010)
- Double Patterning Readiness: Technical and Economic Considerations (Sep 16, 2010)
- Articles Archives