IC Nanometer Design News & Industry Articles

Aug 26, 2010

Aug 9, 2010

Mentor Graphics’ Olympus-SoC Place and Route System Now Supported by X-FAB (Jun 15, 2010)
Mentor Graphics Provides Comprehensive Verification Support in TSMC Analog/Mixed Signal Reference Flow 1.0 (Jun 14, 2010)
Mentor Graphics Extends TSMC Reference Flow 11 with Support for ESL and Integrated Design and Manufacturing Closure (Jun 14, 2010)
Mentor Graphics Collaborates with GLOBALFOUNDRIES on Advanced Design and Manufacturing Flow Based on Calibre (Jun 11, 2010)
Mentor Graphics Works with TSMC to Speed SoC Verification with Calibre Automatic Waivers (Jun 10, 2010)
Mentor Graphics Announces Calibre xACT 3D for Fast and Accurate Extraction Using 3D Field Solver Technology (Jun 8, 2010)
Mentor Graphics Calibre Co-Development of TSMC’s iLVS Simplifies Modeling of Advanced Devices for Physical Verification (May 27, 2010)
Mentor Graphics Calibre InRoute Delivers True Manufacturing Signoff During Physical Design Closure (May 3, 2010)

Waving Goodbye to Phantom DRC Errors (Apr 1, 2010)
The Paradigm Shift in Parasitic Extraction (Apr 1, 2010)
IC Design Flow Must Evolve For Challenges of 28nm and Below (Mar 29, 2010)
The Problems with SOC Design (Mar 24, 2010)
The New Standard for 32-nm IC Physical Design and Signoff (Mar 11, 2010)
Reducing Power with Advanced Clock Tree Synthesis and Optimization (Feb 22, 2010)
Expert Shootout: Parasitic Extraction: (Feb 12, 2010)
The In’s And Out’s Of Parasitic Extraction (Video) (Feb 11, 2010)
Why pattern matching is essential to complex DRC (Jan 29, 2010)
An EDA company's take on 2010 growth sectors (Jan 13, 2010)
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