Industry Articles
April 2013
For power and performance, Fins or BOXes
Rethinking communications: Automating tapeout review reporting
March 2013
Voltage-Drop Analysis Technique Optimizes MTCMOS Cell Placement For Low-Power Designs
February 2013
Optimizing autonomous IC test without sacrificing precision
January 2013
Hospital Privileges: Fixing DP Errors with Cutting and Stitching
Guidelines For Designing Multi-Voltage ICs
Make The Leap From Test Chips To Production Designs At 20 nm
December 2012
Companies Ramp Up To Move From 20 nm To The Next Node In 2013
October 2012
Challenges of Physical Design Closure
Letters from the Front Line at 28nm and 20nm
May 2012
Mentor Graphics Helps eoSemi Solve the Challenge of Silicon Oscillator Design
October 2011
A Quadrant-XYZ Routing Algorithm for 3-D Asymmetric Torus Network-on-Chip
June 2011
Circuit Simulation and IC Layout update from Mentor at DAC
February 2011
Evolution of manufacturing closure for advanced nodes (Part 2)
December 2010
Whither interoperability: The myth of the grand, unifying EDA database
November 2010
New IC verification techniques for analog content
Seven Essential Principles of Analog BIST
22nm-node logic lithography at the boundary of the resolution limit
The Future of IC Design Verification
September 2010
Evolution of manufacturing closure for advanced nodes (Part 1)
Double Patterning Readiness: Technical and Economic Considerations
Seeing Is Believing! How Visualization Simplifies IC Design Rule Checking
Optimizing the Manufacturing Test Program, Data Collection, and Diagnosis for Yield Analysis
August 2010
DRC/DFM Signoff During Physical Design Provides Faster Time to Closure
July 2010
Pattern matching to improve IC manufacturability
Avoid throwing darts at a black hole by using diagnosis-driven yield analysis
June 2010
A New Role for Place and Route: Manufacturing Signoff
Design-then-fix no longer works, says Mentor
Using DFM for Competitive Advantage
May 2010
Designing for 22nm RDRs or DFM?
Calibre Pattern Matching: Picture It Match It... Done
The multicore and EDA road ahead
April 2010
Waving Goodbye to Phantom DRC Errors
The Paradigm Shift in Parasitic Extraction
March 2010
IC Design Flow Must Evolve For Challenges of 28nm and Below
The New Standard for 32-nm IC Physical Design and Signoff
February 2010
Reducing Power with Advanced Clock Tree Synthesis and Optimization
Expert Shootout: Parasitic Extraction:
The In’s And Out’s Of Parasitic Extraction (Video)
January 2010
Why pattern matching is essential to complex DRC
An EDA company's take on 2010 growth sectors
The Paradigm Shift in Parasitic Extraction
EDACafe Video: New Approaches to Parasitic Extraction
November 2009
Confronting Manufacturing Closure at 32 nm and Below
Accelerate Design Closure with Multi-Core Timing Analysis and Optimization
October 2009
September 2009
Pravin Madhani, GM Place & Route Division, talks shop with John Donovan of Low-Power Design
SoC and Analog/Mixed Signal Challenges - EDACafe DAC Video Interview
August 2009
Pravin Madhani speaks to Graham Bell about what’s new with Olympus-SoC
July 2009
IPL Alliance Announces 3rd Annual Lunch Workshop at DAC on Tuesday, July 28, 2009
June 2009
The Design and Verification Challenge for the Next Decade
April 2009
Olympus-SoC Place-and-Route Platform Adds Advanced Low-Power Features
December 2008
Mentor’s new DRC tool targets 32-nm node
Connecting design and fabrication
2008 BEST products award: Olympus
Low Power Designs with Multi-Vdd Flows
November 2008
We switched from Hercules to Calibre for Equation-based DRCs
Design-for-Manufacturing im Nanometer-Bereich
Challenges in 45nm Physical Design
Interview w/S. Jilla: Deep Submicron Designs Challenge Physical Implementation Tools
October 2008
Boatload of users talk up Mentor Sierra MCMM P&R
Programmable electrical rule checking
September 2008
How equation-based DRC solves design/manufacturing challenges
Manufacturing Concerns Move Up the Design Cycle
A Comprehensive Approach to Manufacturing Variation
Interview with S. Jilla: Play It Again, Sam - Consistency of Place and Route When Multi-Processing
August 2008
TSMC Adopts Mentor Graphics Eldo Analog Simulation Tool - EDA Geek News
July 2008
Multi-core Hits EDA Software at Its Core
Reducing time in IC physical verification
June 2008
Minimizing the Effects of Manufacturing Variation During Physical Layout
Multi-Corner, Multi-Mode Power Closure: The New Dimension in IC Design
April 2008
Multi-corner multi-mode designs are no mean feat
February 2008
Improve productivity at nm nodes with faster physical verification
January 2008
Correct-By-Construction Layout Generation And Modification
Applying an Integrated Approach to Mixed-Signal SoC Verification
Probabilistic approach helps ensure DFM success
Doubling Down: Design-Side Issues of Double Patterning
Parasitic Extraction Challenges for Designing Advanced Process ICs
May 2005
Guidelines to Maximize the Performance of Verilog-AMS/VHDL-AMS Behavioral Modeling
April 2005
April 2004
Design for Manufacturing Must Move up in the IC Flow
March 2004
A New Definition of Fracturing
January 2004
Design-for-manufacturing demands new infrastructure
GDSII-based flow speeds mask data preparation
July 2003
The Glue In A Confident SoC Flow
Turning Up The Yield - IEE Electronics Systems and Software
December 2002
Mixed-signal design flow enables RF CMOS chip
Another way around monster mask costs
November 2002
August 2002
Mentor Unveils Big Mixed Signal Play
The Future of Extraction in Mixed-Signal Design
July 2002
Solutions for Maximizing Die Yield at 0.13 Micron - Solid State Technology
The Power of One: Eliminating the Problems of Dual Physical Verification Flows
June 2002
What designers should know about RET
April 2002
Single tool serves IC verification best
January 2002
Choosing a Fast, Smart and Accurate LVS Tool
September 2001
Simulation Tool Models And Verifies Timing Jiter In Oscillators - MICROWAVES & RF
Optimal insertion points for OPC and PSM in design flows
April 2001
Technique will change chip design, speakers say
March 2001
IC Design Press Releases
- Mentor Graphics Pyxis Platform and PDK Automation Process Adopted by MagnaChip Semiconductor (May 14, 2013)
- Mentor Graphics Deep Submicron Division Launches the Kronos Cell Characterization and Analysis Platform (Feb 27, 2013)
- Mentor Graphics Announces Comprehensive Design Enablement Platform for Samsung’s 14nm IC Manufacturing Process (Dec 21, 2012)
- Mentor Graphics Pyxis Platform Applauded by HP (Dec 19, 2012)
- Mentor Graphics Announces that ON Semiconductor Completed Multiple Successful Tapeouts Using Pyxis Custom Router (Nov 8, 2012)
- KALRAY Completes 256-processor, 28nm SoC Design Using Mentor Graphics Design and Test Tools (Oct 23, 2012)
- TSMC Presents Two Partner of the Year Awards to Mentor Graphics for 20nm and 3D IC Design Flows (Oct 16, 2012)
- Mentor Graphics Provides Design, Verification and Test Solutions for TSMC’s 20nm Design Infrastructure (Oct 15, 2012)
- Mentor Graphics Provides Design, Verification, Thermal and Test Solutions for TSMC’s CoWoS Reference Flow (Oct 15, 2012)
- Mentor Graphics Calibre LFD Signoff Litho Checking Tool Certified for TSMC 20nm Process (Sep 12, 2012)