IC Nanometer Design

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IC Nanometer Design Industry Articles

2008

IBM Qualifies Mentor's 45-nm tools Feb 26

2005

2004

Enhancing Manufacturing Test and Yield in the Nanometer Aug 24
Nanometer IC Design: The Altered State of DFM Jun 07
Design for Manufacturing Must Move up in the IC Flow Apr 14
Silicon Modeling in the Nanometer Era Mar 04
A New Definition of Fracturing Mar 01
Lithography: The integration of TCAD and EDA Feb 01
Design-for-manufacturing demands new infrastructure Jan 15
GDSII-based flow speeds mask data preparation Jan 09

2003

A Little Light Magic, IEEE Spectrum Sep 01
The Glue In A Confident SoC Flow Jul 21
Turning Up The Yield - IEE Electronics Systems and Software Jul 08
Addressing mask costs Jul 01
Simulators Shred the Limits of Mixed Signal Designs Jun 01

2002

Mixed-signal design flow enables RF CMOS chip Dec 12
Another way around monster mask costs Dec 09
Follow the Golden Rule Files Nov 22
Mentor Unveils Big Mixed Signal Play Aug 26
The Future of Extraction in Mixed-Signal Design Aug 21
Solutions for Maximizing Die Yield at 0.13 Micron - Solid State Technology Jul 24
The Power of One: Eliminating the Problems of Dual Physical Verification Flows Jul 15
What designers should know about RET Jun 05
The 39th DAC Design the "Big Easy" Way - EDN May 15
Single tool serves IC verification best Apr 02
Choosing a Fast, Smart and Accurate LVS Tool Jan 07

2001

2000

ASML Masktools offers scattering-bar IP for use with Mentor Graphics' Calibre software Feb 29

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