Technique will change chip design, speakers say

ROHNERT PARK, Calif., EE Times — Chip designers who think they won't be impacted by the resolution enhancement techniques (RET) required for very deep-submicron chips may be in for a surprise, according to three speakers at the International Symposium on Physical Design (ISPD). Speakers from IBM Corp., Motorola Inc., and Mentor Graphics showed that RET will have a profound impact on physical layout and verification.

RET is required below 0.18 micron, because a chip's critical dimensions are smaller than the wavelength of light that today's steppers use to print them. The mask data must be altered so that features will be printed correctly, and there are several techniques for doing so.

"The GDSII that's taped out represents what the designer wishes, but there's a big gap between that and what actually happens," said Warren Grobman, director of lithography at Motorola. "You have to understand the mask-making process to know how to modify your GDSII so that what you put into the mask shop gets you what you want."

One common technique described by Grobman is optical proximity correction (OPC), in which shapes are added to the mask so that features are printed correctly. While rule-based OPC can preserve hierarchy, Grobman said, model-based OPC cannot, and requires a flattened database.

Another common technique, phase-shift mask (PSM), uses phase modulation to increase contrast and improve resolution. PSM, Grobman noted, places constraints on the physical design geometry. Scattering bars represent another technique, in which sub-minimum size resolution features are added to the mask.

Tiling is an approach that improves planarity by adding new shapes or "tiles" to sparsely populated areas. Grobman said that model-based tiling can provide an 80 percent uniformity. But it's not innocuous. "When you add tiling to metal layers, you've just taken your design and added metal to your metal," Grobman said. This, he said, may require another verification run.

Grobman said that designers will need to provide mask and wafer process models to make silicon-versus-layout comparisons possible. "We're going to need something different from GDSII," he said. "We ought to have a dialogue about how real the design problems are, and what we do with the design tools."

Frank Shellenberg, strategic marketing manager for Mentor's physical verification business unit, offered some further perspectives on OPC and PSM. He also talked about the impact of off-axis illumination (OAI) techniques that use a shaped illuminator to direct light onto a photomask. These techniques include annular, quadrupole and dipole illumination.

"RET is not done in isolation," Shellenberg said. "There are impacts on design rules and layouts."

One might assume that a manufacturing technique such as OAI wouldn't impact layout, but that's untrue, Shellenberg said. "There are all sorts of strange rules that are already impacting library generation," he said. For instance, some intermediate pitches and feature sizes are not allowed, and 45-degree lines may be poorly printed.

OPC "changes layout dramatically," but the design itself isn't changing, Shellenberg said. The primary impact, he noted, is on verification.

Shellenberg said there's some debate over whether PSM should be introduced early during layout, which would require modified design rules, or delayed until the last possible moment. His suggestion is to adopt phase-compliant design rules, but to delay phase assignment until final verification.

Whatever the technique, Shellenberg stressed the importance of preserving a "target layer" that retains the designer's original intent. He said that many legacy designs contain some OPC that was added to an earlier library, and designers often end up adding more OPC to the previous OPC, ending up with "god-awful shapes." This could be avoided, he said, if a target layer can be used as a reference.

Fook-Luen Heng, member of technical staff at IBM's T.J. Watson Research Center, talked about his company's experience with alternating phase-shift masks (AltPSM). It can effectively double the resolution of an optical lithography system, but not without cost, he noted.

"When you use AltPSM it affects every part of the design process," Heng said. "Designers need to know it intimately."

Heng said that AltPSM can have a density impact of up to 6 percent and a resource impact of 10 to 20 percent. There are "forbidden topologies," such as T-junctions. Spacing conflicts can also be an issue. Thus, Heng said, "AltPSM legalization" becomes a serious challenge.

IBM uses "marker shapes," which are shapes derived from original layout shapes, to identify the conflicts. There are several approaches to resolve conflicts. One involves the use of phase-breaking blocks to break unwanted interactions between phase shapes. Another is increasing the width of critical features, and a third is increasing spacing between critical features.

"AltPSM legalization is more of an art than a science," said Heng. "We need a well-thought out AltPSM methodology and a new set of tools to handle it."


Author: Richard Goering