EE Times, 1/15/2004 - Until recently, predicting IC yield was fairly straightforward: If you could manufacture each structure, you could manufacture the entire chip. The design that was drawn was the one printed on the wafer. The only insight designers had (or needed) into yield issues appeared in design rules with simple DRC yes/no, pass/fail criteria. But as designs have grown more complex, process technologies smaller and geometry counts higher, the work required to achieve acceptable yield has become increasingly demanding and difficult.
At 180 nanometers, newer issues, such as planarity and antennas, began to dominate yield loss. The DRC model was extended to encapsulate them. Now manufacturing has changed even more radically. Long gone are the days of "print as drawn."
The number of yield-limiting issues can no longer be confined to a small set of constraints. Foundries have been applying postlayout resolution-enhancement technologies since 180 nm in order to manufacture the design as close as possible to drawn. Even at 130 nm, designs that are verified as "DRC clean" can still result in poorly yielding or even nonfunctioning silicon. Although a specific design element or configuration in and of itself can be physically manufactured, it may in the context of a particular full-chip layout dramatically increase the probability of failure.
As companies move to 90 nm and smaller, the need for managing yield issues and adopting design-for-manufacture (DFM) methods will be greater than ever. Because improvement in manufacturability must be weighed against the effects on performance, size and functionality of a design, designers will need to be involved in analyzing the variables that contribute to these design specifications. This means that manufacturability must start at the chip design level.
It is not enough however, as some have suggested, to merely include DFM specifications in automated place and route tools. This method does not address how various components will react to each other when integrated in a full chip. As in traditional DRC manufacturing methods, DFM methodology must incorporate a full-chip approach; that is, data must be made available in its full context. This means having access to yield-limiting issues in a cross-layer and cross-hierarchical sense. Being able to look across hierarchical boundaries to see how the data in one cell interacts with data outside the cell is essential. It may be possible to improve the manufacturability of one layer by manipulating another. Similarly, a cell with no known manufacturability issues may significantly affect the manufacturability of a full chip when it is placed into context.
This more comprehensive model requires a new infrastructure that supports a feedback loop between designer and manufacturer. The feedback loop will include a means of defining and relaying manufacturing constraints, verifying IC layouts and addressing manufacturing-related issues to the designer. To make this feedback loop more intuitive for the designer, an integrated solution is needed that bridges the postlayout GSDII environment and the design layout environment-a solution with read and write capabilities in the design database format, the ability to annotate edits or changes back to the design environment and access to design analysis tools. Within such a bridge, the designer will be able to implement postlayout changes in the original layout environment, and will gain the ability to reanalyze and verify the impact of changes created. The bridge will also provide a method of retaining intellectual property that is more yield-compliant.
Naturally, the industry seeks a methodology that produces designs with superior layout yields by construction. But this in itself is not sufficient. An independent platform for identifying the remaining issues after creation, as DRC has supplied, is still required, as is a method that allows the designer to make improvements based on what he or she finds. And once this independent platform hands back the information on the issues, the designer can initiate a three-step process for making the decision to "fix or fab"-access all data, implement layer analysis and gather feedback.
Fortunately, the core technologies required to build this design-for-yield flow exist now. Tools capable of reading and analyzing layout topography so as to preserve hierarchy for upstream and downstream analysis are currently available, with existing links to many design environments. The only new requirement is a more robust communication mechanism that allows designers to understand impacts and make decisions on trade-offs.
A complete data, layer-analysis and feedback methodology will let designers make decisions and take control over which issues will be corrected and in what way. Implementing an infrastructure that provides designers with vital yield information to determine the best course of action will result in a yield greater than that achieved by simply meeting process design rules and using engineering best practices.
John Ferguson is product-marketing manager at Mentor Graphics Corp. (Wilsonville, Ore.).
