EDAVision Magazine, August 2002 - Traditionally, parasitic extraction tools are customized to handle the requirements of a specific design flow. This specialization forces system-on-chip (SoC) designers to either maintain multiple tools or use functionality that is unsuitable for a variety of design styles. However, analog/mixed-signal (AMS) SoCs have created a whole new paradigm for parasitic extraction that necessitates mixed-level analysis. The design styles found in AMS SoC designs, be they analog, memory, full custom, or others require a very comprehensive approach to extraction.
Today's AMS SoC designs can fail if the parasitic effects of passive interconnects are not addressed. These effects are not only significant for timing, but also for power, reliability and noise. Detailed analysis requires much more than a traditional extracted SPICE netlist or timing file. AMS SoCs require a comprehensive approach to parasitic extraction, including:
- Accurate extraction algorithms to model interconnect effects on today's advanced processes
- Tight integration into the design environment to ensure efficient data handling for both upstream, design creation environments, and downstream post-layout analysis
- Advanced data management to handle the enormous amount of parasitic elements that are extracted from current SoC designs
Accurate Extraction
In AMS SoC designs, all nets could be critical. For sensitive analog portions of the circuit, small nets on the order of attofarads need to be accurately extracted with full coupling effects. At the full-chip, the parasitics for large nets such as the clock net or power and ground need to be accurately modeled. Therefore, next-generation extraction needs to provide field-solver-like accuracy to both large and small nets for capacitance and resistance extraction.
Furthermore, advanced manufacturing techniques place additional requirements on the extraction engine. Processes today may include conformal dielectric layers, copper wiring and non-rectangular cross-sections that need to be modeled correctly to determine interconnect effects.
Integration with Layout Versus Schematic and Mixed-Level Extraction
AMS SoC designers need to be able to integrate parasitic information into their design environment. Post-layout information needs to be integrated as an entire circuit or subcircuit suitable for simulation. To enable this, a tight integration with the layout vs. schematic (LVS) tool is required to create a final netlist or view ready for downstream analysis. The tools need to provide accurate intentional device recognition for the variety of devices (transistor, inductor, capacitor, varactor, etc.) that will be implemented in today's AMS designs. The intentional devices need to be incorporated with the parasitic data to provide the most complete representation of the circuit possible. Also, the data out of the LVS/extraction tool needs to back-annotate to the source schematic. This enables the designer to employ the same test vectors on the post-parasitic netlist or view as were used for simulation of the source. Finally, graphical browsing of all the data (device, parasitic, layout, etc.) can enable debugging of parasitic or analysis results.
Advanced Data Management
SoC designers have the challenge of attempting to implement a number of different circuit element types that have a myriad of post-layout analysis requirements, ranging from transistor-level, gate-level and hierarchical simulators that require parasitic data in various formats and levels of granularity.
Using an extraction tool that operates in a "one-run" incremental fashion can save countless hours. "One-run" means necessary data is quickly extracted once and stored in a binary format. Then, designers can select between transistor, gate, hierarchical or select net results and send the data to be analyzed to different tools such as static timing or voltage drop analysis with zero time wasted in repeated extraction runs.
The future of the industry calls for best-in-class extraction technology in a single tool for the full range of design styles found in AMS SoC designs, be they analog, memory, full custom, or others. This will include accurate extraction, mixed-level extraction and superior integration with LVS, and advanced data management for faster extraction.
Carey Robertson is product marketing manager for Calibre extraction tools at Mentor Graphics Corp.
