Choosing a Fast, Smart and Accurate LVS Tool

Electronic News, 1/7/2002 - Employing EDA advances in layout vs. schematic (LVS) technology is critical for designers keeping pace with complex IC demand. Today's system-on-a-chip (SOC) designs and multimillion-transistor circuits are incredibly complex, containing enormous amounts of specialized data and deep-submicron effects. Additionally, competitive, time and manpower pressures present traditional verification with serious shortcomings. Reliance on human analysis to properly identify and repair errors on complex circuits simply cannot assure working silicon.

Although current LVS tools efficiently alert designers to layout-based problems, error diagnosis remains a concern. Recent industry estimates predict that as a result of ever-increasing complex circuit designs, up to 75 percent of a designer's project time can be spent in verification. Users of traditional LVS tools must rely on complex texting and frustrating guesswork to accurately identify the source of errors. The biggest danger in using a text-dependent LVS debug tool is that a circuit may read as clean in verification, yet will not work in silicon. Although texting can be useful as an aid, it does not represent or play a role in the true electrical behavior of a circuit.

Yet without texting, users of traditional LVS tools have difficulty tracing the source of errors. If a designer incorrectly interprets or strays from the texting output, one single net mismatch may result in the reporting of many net and device mismatches. Discovering the true source of the problem requires an in-depth understanding of the tool's algorithms, electrical connectivity of the layout and the intent of every portion of the original source design.

Choosing between a flat or hierarchical tool also presents problems. Flat LVS tools view every layout net and device as unique: one error instantiated many times can show as many errors. An instantiated error may limit the tool's ability to properly identify the correct nets and devices associated with it. Hierarchical LVS offers significant advantages over flat LVS by viewing each instantiation as unique.

Meeting the Challenge of LVS
With the challenges of complex circuitry and SOC, employing an LVS tool that relies more on electrical behavior models and less on human labeling is essential. It must intelligently pinpoint errors through an intuitive graphical interface and more accurate and usable textual reports. It must provide an integrated, cross-probing environment. Finally, it must offer a highly productive means to rapidly locate and repair flaws.

Fortunately, innovations in design automation technology make all of this possible. Today's advanced LVS tools offer seamless integration in popular layout environments and employ graphical user interfaces that are powered with more intelligent algorithms to provide highly accurate error identification.

Smart algorithms return LVS mismatches only for physical locations and hierarchical components where real errors exist, allowing designers to quickly address actual errors and avoid wasting time. Tools with sophisticated algorithms can isolate difficult power/ground shorts in minutes. In combination with 64-bit processing and large data capacity, smart algorithms accommodate complex designs.

An LVS tool incorporating both hierarchical and flat comparison capabilities is a far better solution than an LVS tool that is either strictly hierarchical or flat. Cell libraries, memory blocks and other intellectual property elements have obvious matches between the source and the layout. By allowing these blocks to be compared in a hierarchical manner, while allowing other design elements such as analog blocks and macro cells to maintain a flat representation, debug performance is drastically enhanced, and flow management problems are avoided.

Quick and successful debugging can happen only if the LVS tool is intuitive and foolproof. Tight linkage between LVS, common layout editors, schematic capture tools and a netlist browser within an integrated environment allows the designer to cross-probe, pinpoint and correct errors with intelligence and precision. And an LVS tool that works from GDSII layout and SPICE netlists, which are global foundry standards, assures a high rate of success at the manufacturing level.

Author: John Ferguson is the technical marketing engineer at Mentor Graphics Corp., based in Wilsonville, Ore.