Mentor Unveils Big Mixed Signal Play
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ELectronic News, 8/26/2002 - Mentor Graphics is launching several new tools today that it says come together as a front-to-back custom IC design flow. The move is sure to turn the ongoing battle between Mentor and Cadence Design Systems in subsets of the flow, such as mixed language, transistor-level simulation and physical verification, into something close to war.
Wally Rhines, chairman and CEO of Mentor, will be in Silicon Valley today to stand up with top customer STMicroelectronics and a few undisclosed others to talk up the tools. Rhines said Mentor has a whopping 90 customers for the so-called ADMS flow. Twenty of those customers are new this year, and four of those just added this quarter. The numbers for new customers are impressive given the macroeconomic environment, which is so bad that last week Synopsys revised its guidance downward for the year and reported a $138 million loss for the quarter. "The buying environment is bad," Rhines said last week in an exclusive briefing before the big rollout. "People are only buying if they are desperate, and they are desperate. They are desperate to be able to introduce the next generation of mixed signal designs." And they need an integrated design environment to do that, he added. "What you can do now is start your design with any number of sources—any Verilog or VHDL block, any schematic—and do full top-down simulation and then do a full bottom-up verification," Rhines said. The transistor-level- and digital-block parasitic extraction comes in the new Calibre xRC functions, and the fast transistor simulation comes from a new integration of Mentor's Mach TA tool into a new hierarchical design environment. Here, Mentor is leveraging its dominance with Calibre, especially with the legion of fabless customers at Taiwan Semiconductor Manufacturing Co. (TSMC). Gartner Dataquest puts the tool's market share somewhere north of 85 percent. "Calibre is such a de facto standard," Rhines said. "Why not just use Calibre xRC for transistor-level and digital extraction? Why integrate with a tool that can't do that?" Rhines argued that Cadence would be playing catch-up with the Mentor ADMS flow now hitting the streets. "Nothing I'm talking about today is a promise for the future," Rhines said. "There are enhancements that we are announcing, but all of them are immediately available. "Cadence has talked about it," he said. "But it's still something on their roadmap." Rhines said what's happening in the semiconductor industry today is a phenomenon economists call the "flight to quality." Semiconductor makers are engineering the 90nm process node to let them build much higher margin mixed signal devices, such as cell phone SOCs that can directly convert RF signals to the digital baseband. "It used to be if you tracked process introductions, the new design rules were introduced in digital technology typically a couple of years before analog and other enhanced equivalents were. Now it's running about a quarter behind and showing signs of moving in parallel," Rhines said. "That changes what has to be available (from EDA vendors) to support a new process and a design flow." And it's the higher margins for these mixed signal SOCs that have driven manufacturers to demand so much of their 90nm fab lines and test floors. "Years ago I talked to people about the potential there," Rhines said. "You can have a $5 digital ASIC combined with another $5 analog chip, or you can have a $25 mixed signal chip. Now the multiples aren't quite so high; but even so, it's a lot better than digital alone can do." |