EE Design, 7/5/2002 - Unknown to most IC designers, IC layouts have been undergoing a dramatic revolution in recent years. This is happening because, in order to meet the increasingly aggressive requirements of Moore's Law, creative refinements for lithography technology are being taken off the shelf, reexamined, and employed where useful. So many optical "tricks" (more technically called Resolution Enhancement Techniques, or RET) are now employed that the layout on the reticle looks dramatically different than the layout desired on the wafer. The what-you-see-is-what-you-get (WYSIWYG) world of IC design, mask making, and fabrication is coming to an end.
This did not happen overnight. Almost 10 years ago, Moore's Law was laid down in a document that has evolved to be the International Technology Roadmap for Semiconductors (ITRS, or more commonly, the Roadmap). The Roadmap started as a process to synchronize tool research and development with forecast technology demands. What was unanticipated, however, was that this Roadmap would become viewed as the baseline for "average" technology - and of course, all advanced IC manufacturers had every intention of being "above average," like the children of Lake Wobegon fame. They set their internal schedules more aggressively to "beat the roadmap."
Thus, when the Roadmap came up for revision, the new aggressive targets became the new industry "average" and therefore a new team to beat. A vicious circle of technology was ignited that has led to a three-year acceleration of the roadmap, rather than a stable, predictable development timeline. The final result is that ICs with target dimensions under 100nm will be in limited production by the end of this year, not in 2006, as the earliest Roadmaps predicted.
Around five years ago, the ever-increasing demands of Moore's Law and the accelerating Roadmap caused the IC feature dimensions (gate and DRAM half-pitch) to become smaller than the wavelength of light used for lithographic patterning of these features. This was previously viewed as an insurmountable barrier that would require the adoption of radical short wavelength technologies (such as x-rays, with l=8-13 nm, or E-Beam lithography, with DeBroglie wavelengths orders of magnitude smaller) to achieve their goals.
However, through the creative use of image manipulation techniques, optical interference effects and phase-shifting masks, high quality patterning can occur even at half-pitches of l/4. Many of these RET approaches have their roots in theoretical optics papers published at the end of the 19th century, and had been further explored in optical niches such as holography in the second half of the 20th century. The application to lithography was first recognized in research labs around 1980, and after occasional waves of development and demonstration, these techniques were well documented and on the shelf, waiting when the sub-wavelength barrier began to draw near.
There are three main RET approaches, each addressing an independent variable of the optical wave: direction, amplitude, and phase.
Figure 1 - RET variables
Off-axis illumination (OAI) improves resolution by illuminating the reticle with light off the optical axis of the stepper lens. The interaction of light at an angle, falling on mask structures that are essentially diffraction gratings, can improve the contrast of the image by transmitting more of the diffracted orders through the lens.
Figure 2 - Off-axis illumination
Optical and Process Correction (OPC) changes the size of openings in the reticle by small jogs and the addition of serifs and sub-resolution features. This allows more or less light to be transmitted through the mask so that the image after diffraction matches the desired pattern.
Phase-shifting masks (PSM) alter the phase of light passing through different portions of the mask, creating regions of destructive interference in the image with higher contrast. These dark fringes can be extremely narrow, since there is no limitation for a wavelength of "dark," only for a wavelength of light.
These techniques can be used individually but are far more commonly used in combinations. These include attenuated phase shifters that also require OPC and yet enhance contrast, off-axis illumination combined with certain styles of sub-resolution OPC to tune the diffraction pattern for highest efficiency, and twin chrome-less phase edges exposed with off-axis illumination to enhance the process window.
Process engineers are still getting used to this "sub-wavelength" regime, exploring which combinations of these tools work best with different design styles. One result not originally anticipated with the original demonstrations of enhanced resolution is the unwanted prohibitions on design layouts that can arise.
With OAI, repeating patterns at certain dense pitches can be significantly enhanced and new targets in the Roadmap achieved, but larger, more pedestrian pitches can fail dramatically when OAI is adopted. These "forbidden pitches" have been characterized now for a number of processes, and will be unique to each combination of process conditions and stepper illuminator design.
Figure 3 - Forbidden pitches
With OPC, the small jogs and serifs that decorate a layout after OPC can create a challenge for a mask maker. Although some of these will indeed improve the image fidelity, sub-resolution features that are too small simply cannot be created on contemporary mask making equipment, and additional checking steps for the mask layout are required to insure manufacturability.
Figure 4a - Small jogs and serifs
Figure 4b - Small jogs and serifs
With PSM, a whole new world of design rules is created. The destructive interference between regions of opposite phase is a huge boon to resolution enhancement, but there are certain common geometric shapes where this simply cannot be easily used - at critical-CD T-junctions, for example.
Figure 5 - T-junctions
To allow opposite phases on one line of a T, some special trick must be employed to insure that the other side of the T can still be manufactured. A common way out is to use double exposure, where an additional mask is created to eliminate unwanted artifacts of a first exposure (a so-called "Trim Mask"). With a single layer now represented by two different masks, one and possibly both colored with regions assigned to different phases, the mask layout is very, very far away from the original designer's intent for the wafer.
Double exposure inevitably means a throughput hit for the processing equipment. However, once that value has been calculated and weighed against increased performance, several double exposure techniques have been taken off the shelf and reexamined. One example is dipole illumination, in which light falls on the mask from only two opposite sides. This can achieve extreme enhancements of resolution for lines perpendicular to the dipole orientation, and recently 90 nm line/space pairs were reported using 248 nm exposure wavelengths. However, for the other orientation (parallel to the dipole), imaging fails completely. This lack of symmetry was the reason dipole was put on the shelf 10 years ago in favor of other off-axis techniques.
Now that the sub-wavelength regime is here, this technique is being pulled off the shelf, and being reexamined. To achieve a full layout, two complementary exposures are needed, one for vertical lines and the other for horizontal lines. This becomes tricky when layouts include other orientations as well (such as 45-degree lines), which requires sophisticated data parsing algorithms and OPC to be applied.
Figure 6 - Two exposures
Figure 7 - Wafer elbow after double exposure
However, when the competitive techniques are more expensive, these problems seem far more manageable in comparison. Scripts to implement data parsing algorithms are in test at Mentor Graphics, dipole hardware is now commercially available for ASML scanners, and experimental results have been reported by TSMC and others.
Lithographers implementing these new RET combinations have been able to do amazing things - 110 nm Line/space pairs with 248 nm light, individual transistor gates as small as 90 nm, and even smaller using PSM and additional processing tricks. Optical solutions now seem capable of delivering the current Roadmap forecast for the next seven years, unless the Roadmap goals are pulled in yet again!
Lithographers encounter conflicts between design layouts and RET on a daily basis, however, and call for the day when designers will learn more about the new era of lithography. Lithography consultants are excited by the prospect of full enrollment in classes filled with designers learning the basics of RET. At the most recent SPIE Microlithography conference, a new sub-conference specifically to address "Design and Process Integration" was held and well attended - by lithographers. Unfortunately, aside from a few EDA vendors with commercial interest, there was nobody with design credentials to be seen at this forum. Instead, they are all making plans for DAC.
The design community, of course, remains blissfully ignorant of this activity on design and process integration, and for good reason. Most design firms are now fabless, and became fabless so they wouldn't have to deal with this level of process detail. Design rules are downloaded from their foundry website; if they follow those rules, it then becomes the foundry responsibility to make things work.
This reluctance to change a paradigm has driven large portions of the lithography community to make an initial investment in frighteningly expensive extreme ultraviolet (EUV) lithography (l =13 nm), which is supposed make these problems go away by placing us comfortably back above the sub-wavelength regime - for now. However, at a forecast cost of $100M per scanner, using masks that may cost $100,000 each, a fab using these had better be producing a very high margin per wafer. Most medium volume designs will not meet these criteria.
The gap between these communities seems to arise because a paradigm for communication between the process world and the design world which used to work well - the Design Rules -is unable to carry enough information to allow the entire system to be optimized. Yet, given the historical tendency, neither side has shown great motivation to break out of their classical paradigm.
What is evolving to fill this gap is a new generation of EDA tools, which communicate with standard EDA formats, but include internal algorithms and simulators tuned to the process requirements of RET. Library generation tools that produce RET compliant layouts, such as those recently discussed by Prolific, are a step forward in this direction. The addition of process simulation to layout verification tools, as has been done in Mentor Graphics' Calibre suite, again allows process effects to be automatically predicted and flaws reported as potential design rule violations, using the same interface familiar from normal DRC checks.
As these tools implementing RET compliant knowledge become standardized, the information they require will also become part of the standard package to be downloaded along with the classical design rules. In this way, the "paradigm" is not challenged, only the contents of the information package have changed. Designers will not need to take seminars on diffraction, and lithographers will not need to learn how to debug RTL. Each professional group can remain focused on doing what they do best, as long as the tools continue to evolve to fill this gap.
F.M. Schellenberg received his Ph.D. from Stanford University in Applied Physics, and spent 12 years working at the IBM Almaden Research Center. He has since worked at HP Labs and Sematech, managing the development of new OPC technologies and sponsoring the formation of several OPC related start-ups. He has also worked at KLA-Tencor, managing projects in the reticle inspection technology and analysis, before joining the OPC start-up called, appropriately, OPC Technology. This was acquired by Mentor Graphics in 1998, and Schellenberg now works for the Calibre verification product group of Mentor Graphics.
