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Mentor Graphics Design-to-Silicon Solutions Used in Successful Development of TSMC 28nm Product Qualification Vehicle Test Chip

WILSONVILLE, Ore., August 9, 2010 – Mentor Graphics Corporation (NASDAQ: MENT) today announced that its Calibre® Design-to-Silicon solutions were key elements in the successful development of TSMC’s 28nm Product Qualification Vehicle (PQV), a major milestone in the TSMC process development. Multiple Mentor products were used in the design of the PQV test chips, including the Calibre nmDRC and Calibre nmLVS tools for design verification, and Tessent™ test suite for silicon test.

“Mentor has a robust design and implementation track in TSMC’s Reference Flow 11.0 targeted to support 28nm design efforts,” said ST Juang, senior director of Design Infrastructure Marketing at TSMC. “In addition, the Mentor Calibre platform has been a key physical verification solution that TSMC supports for multiple process generations. Now we are taking one big step further to extend it into 28nm through PQV collaboration.”

TSMC Reference Flow 11.0 includes a complete Mentor track targeting TSMC’s 28nm process. In addition to the Calibre verification platform, the expanded Mentor track provides a complete front-to-back solution that now includes the Vista™ Electronic System Level (ESL) design and verification platform, the Catapult® C synthesis tool, functional verification with the Questa® platform, expanded low power and 28nm routing features in the Olympus-SoC™ place and route system, and the Calibre InRoute solution, which provides the Calibre platform for signoff analysis and automated repair integrated into the Olympus-SoC physical design environment. Also included in the Mentor 28nm track are the Calibre Design-for-Manufacturing (DFM) and parasitic extraction offerings and the Tessent TestKompress® scan test tool, as well as memory built-in self test, IEEE 1149.1 boundary scan, and test failure diagnosis tools.

“Mentor has worked with TSMC to continuously enhance the Calibre platform so that it is not only a key verification platform for production tape outs, but is also used for advanced process development efforts as well,” said Joseph Sawicki, vice president and general manager of the Design-to-Silicon Division at Mentor Graphics. “We are pleased to be part of this major milestone in TSMC’s 28nm development, and look forward to helping mutual customers release their designs to TSMC’s most advanced process offering.”

About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: www.mentor.com/.

For more information, please contact:

Gene Forte
Mentor Graphics
503.685.1193
gene_forte@mentor.com
Sonia Harrison
Mentor Graphics
503.685.1165
sonia_harrison@mentor.com

(Mentor Graphics, Calibre, Questa, TestKompress and Catapult are registered trademarks and Vista, Olympus-SoC and Tessent are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)

 
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