Mentor Graphics to Deliver Select EDA Technologies To Freescale Semiconductor
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WILSONVILLE, Ore., August 14, 2006 - Mentor Graphics Corporation (Nasdaq: MENT) will supply Freescale Semiconductor (NYSE:FSL, FSL.B) with select EDA technologies designed to enhance the manufacturability and testability of semiconductors. Mentor plans to provide EDA tools in several focused areas of the nanometer chip design flow. The plan includes tools in the areas of Design for Test (DFT), physical verification and analysis, advanced Resolution Enhancement Technologies (RET) and post-tapeout Design for Manufacturing (DFM). The new arrangement expands on an existing collaboration in areas where Freescale and Mentor can develop methods to improve test and manufacturing capability. "In the emerging area of DFM, Freescale continues to invest significantly in order to provide DFM capability at every phase of the chip design process - from Architecture phase to Mask Preparation phase," said Ross Hirschi, Director of Methodologies and Flow Development at Freescale. "This helps to ensure that our chips are manufacturable by design. Mentor's solutions fit well in specific areas of Freescale's comprehensive DFM flow." "Mentor is extremely pleased to enter into this agreement with Freescale, and will work closely with them on our common goal of achieving breakthroughs in semiconductor technologies." said Wally Rhines, Chief Executive Officer of Mentor Graphics Corporation. About Mentor Graphics
Mentor Graphics is a registered trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners. For more information, please contact: Sonia Harrison
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