Mentor Graphics Announces Industry’s First Multi-mode Multi-corner Signal Integrity Solution for 65/45nm
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WILSONVILLE, Ore., December 10, 2007 – Mentor Graphics Corporation (Nasdaq: MENT) today announced new technology in its Olympus-SoC™ place and route product that dramatically accelerates signal integrity(SI) closure and improves the reliability of manufactured silicon. The Multi-Corner, Multi-Mode (MCMM) capability of Olympus’ Static Timing Analysis (STA) engine concurrently computes delay shift and glitch for any number of mode/corner scenarios in a single pass. MCMM analysis enables customers to address reliability issues such as crosstalk delay, glitch, power, and electromigration while reducing the time to achieve design closure. The Olympus-SoC product’s detailed routing and optimization engines have been enhanced to help eliminate SI violations concurrently over all variation scenarios. Customers designing at 65/45nm are experiencing a significant increase in SI related timing violations due to increasing dominance of lateral wire capacitance. An explosion in the number of mode and corner scenarios that must be addressed exacerbates the problem, significantly increasing the time to design closure. Current solutions are severely limited due to inability of the core STA engines to represent more than a single mode/corner combination for SI analysis. This severely hampers design teams who are forced to run several iterations with a lot of manual intervention. Mentor’s Place and Route division has invented a breakthrough technique to concurrently compute and maintain mode/corner-specific delay shift, glitch, power, and electromigration (EM) data in a single analysis run. The solution includes several enabling technologies:
“Multi-mode multi-corner SI closure is a latent design issue that critically impacts design performance and schedules,” said Senthil Krishnasamy, Physical Design Director at AMD. “Mentor’s new MMMC SI optimization technology addresses this issue comprehensively, and we are very impressed with the quality of results and the reduced time to design closure. Olympus-SoC MMMC SI optimization is now a standard part of our design flow.” “AMD is designing some of the world’s most complex chips and we are very happy to partner with them in solving 65/45nm design issues,” said Pravin Madhani, general manager, Place and Route Division, Mentor Graphics Corporation. “Other solutions, including signoff quality timing and SI engines, are critically handicapped because they were designed to handle SI analysis for only one corner at a time. Olympus-SoC’s MCMM SI capability addresses a major unmet need in the design community.” About the Olympus-SoC Product About Mentor Graphics
(Mentor Graphics is a registered trademark and Pinnacle and Olympus-SoC are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.) For more information, please contact: Sonia Harrison
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