Application of Advanced Phase-Shift Masks

Mentor Graphics Corp., San Jose, 9/1/2003 - Almost 20 years have passed since phase-shift masks (PSMs) were proposed to enhance the photolithographic pattern transfer. The most senior PSM option, the alternating PSM (altPSM), has been regarded as the ultimate tool to enhance the resolution of a given lithography setup. However, it has found only limited application for very specific devices. Various other PSM configurations were also proposed, made and evaluated in an evolutional and competitive environment. So far, the halftone PSM (HTPSM) — also called embedded or attenuated PSM (attPSM) — is the only PSM option widely in use for production.

For the 90 and 65 nm technologies under development, more aggressive PSM options will be needed. In the next years, we surely will witness an interesting and exciting next round of evolution. The following is intended for better understanding of the basics and the upcoming challenges.

Evolution of PSMs
Like any other evolution, the PSM evolution has not been a straightforward series of events. Figure 1 attempts to show the lines of development in the context of time (top to bottom) and PSM aggressiveness (increasing from right to left).

Soon after the altPSM was evaluated for the first time, the etching processes developed for it were used to generate phase edges in the vicinity of features. These so-called rim and/or outrigger PSMs did not provide the same improvement in process window as the altPSM, so they were called "weak PSMs." Originally proposed for X-ray lithography, the HTPSM provides approximately the same benefit as other weak PSMs, but is much easier to create. Increasing the transmission of the dark areas of HTPSMs increases the benefit, but also generates unwanted bright features, which in a three-tone PSM (three different transmissions: bright, halftone and zero) are blocked by small patches of chromium.

If in an altPSM the width of a chromium line between two phase regions of opposite phase is reduced to zero, a very narrow dark line is printed. This chromeless or phase-edge PSM has a rather good process window. However, two phase edges in close proximity do not print well unless the printing tool uses off-axis illumination in the chromeless phase lithography (CPL) technique.¹ But "pure" CPL is capable of printing only a rather narrow range of linewidths, even with the help of subresolution assist features (SRAFs), widely used in regular chrome-on-glass (COG) or HTPSM. To print arbitrary patterns, chromium features must be added, yielding the PCO (phase edge, chromium, off-axis illumination) technique.² Figure 2 shows cross sections of masks used by PCO.

One of the most prominent issues of the altPSM is the impossibility to print an isolated resist (dark) line of finite length without using a second mask to expose away unwanted dark features. An alternative is to use regions of intermediate phase (e.g. 60 and 120?) to partition the unwanted 180? phase edges into a series of non-printing phase transitions.

Cost of making PSMs
Although there is usually more than one process flow for making a particular PSM, common strategies such as self-aligned patterning processes have evolved by their merits of simplicity and ease. In addition, the need to agree on common requirements for the maskmaking equipment has forced further standardization. This makes it easier to estimate the cost to make a particular PSM option.

Table 1 provides a rather simplified estimate of the effort to make a certain type of mask, based on the different process steps necessary to make it. The numbers given are in units of a standard COG mask process — for example, 0.5 for high-resolution patterning indicates that printing a mask with a high-resolution tool (which usually has very low throughput, but costs a lot) is about 50% of what it costs to do all process steps for a standard COG mask.

The most expensive mask to make is a mask for PCO, since it requires both the subresolution patterning process for SRAF, and the quartz etch process, and the more complex inspection and repair process to generate defect-free phase regions. But PCO needs only one mask, so the mask component of the lithography process cost for PCO is still smaller than the cost to provide the second trim exposure (usually a COG mask) for altPSM. HTPSM needs a second patterning step to define the chromium shield outside the active chip area. A three-tone PSM needs the same patterning step, but with the same resolution as the first exposure. PCO and altPSM need a similar second patterning step.

The numbers in Table 1 might not reflect those of a specific mask house, since survival strategies of mask houses may lead them to produce price tables very different from what is shown here. However, Table 1 demonstrates clearly that the HTPSM offers the lowest cost and, therefore, is most widely used. As it is even cheaper to make than COG masks with SRAF, the HTPSM has been applied earlier in high-volume production.

Opportunities and challenges
The cost to manufacture different PSM options can be estimated, but maskmaking cost alone cannot predict the most economical way in which to apply a particular type of PSM. The photolithographic community has written extensively on the advantage of one particular PSM strategy over another and, although each published case is valid for the chosen parameters, there are considerations to be made within a larger context.

Table 2 shows an example of a chain of reasoning, how in three different typical scenarios the optimum PSM strategy can be deducted from given priorities. For DRAMs, for instance, design rule shrinks were justified by getting more working chips from one wafer. DRAM masks are used for a relatively large number of wafers, so many improvements pay off.

Most importantly, DRAM design is well integrated with manufacturing, so it is relatively easy to get DRAM designers to agree to certain layout restrictions as long as the chip gets smaller with no impact on overall yield. For all these reasons, DRAM has traditionally been the avant-garde of process development and, in particular, lithography. For the 65 nm node it can be expected that DRAM will be made by rather creative methods of single and/or double exposure with the possible integration of PCO and altPSM.

Logic foundries, on the other hand, have to make whatever the logic designer provides, based on design rules and design rule checks. As complex as those design rules may be, the business process, of which design rules are a part, makes it very difficult to implement certain restrictions, which a newly developed lithography option may demand in exchange for much better process latitude.

The alternative is to refrain from the ultimate resolution possible by a given lithography tool set in order to reduce the chances of an unprintable layout. Since mask cost and total runtime, including maskmaking, are also critical issues for foundries, it is very unlikely that more expensive and time-consuming PSM techniques will be the option of choice. HTPSM plus SRAF (eventually with improved methods to generate SRAF) will remain the most probable PSM solution for quite some time.

The highest priority for a typical microprocessor manufacturer is the speed of the most critical transistors. In lithographic terms, this means that the width of critical gates must be as small as possible, and that variations in that width need to be minimized. In this case, the altPSM is the most appropriate solution, despite high cost and the required double exposure.

However, PCO, which can deliver an almost equal process window as altPSM, but only for a small range of linewidths, can be a much more cost-effective alternative, provided that the range of critical linewidths can be drastically restricted. Because microprocessor design is similarly well integrated into manufacturing as DRAM design, PCO is a possibility.

The process to generate a real-world table similar to Table 2 is of course much more complex than demonstrated. It forces the lithography developer to recruit the active participation of the device and chip designers, as well of those involved in maskmaking, process integration, and fab management. In addition, Table 2 does not consider that most chips designed today are a compound of logic parts and large memory arrays, often with an integrated microprocessor. For these cases, the lithographic demands of each component need to be assessed differently.

However complex and difficult, a few general considerations are common to all lithography process decisions:

• Which layout restrictions are known for the PSM option of choice, and how can it be assured that, at tapeout, only compatible layouts are generated?
• Is the mask manufacturing process of the chosen mask house capable to deliver masks with the required specifications within a reasonable time?
• Switching the masks for an existing lithography tool set from HTPSM to altPSM or to PCO increases the resolution of the process. However, it does not improve the alignment capability of the tool. Can the design tolerate an additional alignment error caused by the double exposure?
• Not all existing steppers/scanners have lenses designed to perform equally well with all PSM options. How large may the additional pattern distortion be?
• The more aggressive PSM options used, the tighter the requirements will be for OPC and for the metrology that OPC relies on.

This last issue, in particular, makes it very important to have a software tool for OPC and the mask data generation that can perform all the required layout polishing steps within one integrated system and within one way to handle hierarchy. Otherwise, mask data file sizes of 50 GB and larger can be easily generated.

Summary
Many different PSM options have been developed, widely discussed and evaluated since PSMs were first proposed for lithography. Every time there is concern about the reliability and/or availability of other lithography options, more PSM applications are considered. By the mid-1990s, HTPSMs had gathered widespread production application, since they deliver a significant benefit at a relatively small cost in manufacturing, data handling and usage.

The late projected arrival of 157 nm and next-generation (non-optical) lithography has again increased the general interest in PSMs. But this time a whole new set of critical issues has to be dealt with to decide on the most appropriate and economical option. These more aggressive PSM options require more and more effort to thoroughly answer with confidence all the questions necessary for these decisions.

In addition, the current surge of fabless companies and foundries decreases the interaction between designers and process people, thereby decreasing the available choices. Creative software solutions will be necessary to provide the feedback from manufacturing and from data preparation into the design realm to fully utilize the potential of advanced PSMs.

Author: Wilhelm Maurer is director of advanced lithography programs for Mentor Graphics . Previously, he was director of optical enhancement techniques in the Lithography Module Solutions Group at KLA-Tencor. He has a Ph.D. in physics and mathematics from the University of Vienna.