Mentor Graphics Collaborates with TSMC to Provide Advanced DFM Capabilities in Reference Flow 8.0
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WILSONVILLE, Ore. and HSINCHU, Taiwan – June 5, 2007 – Mentor Graphics Corporation (Nasdaq: MENT) and Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) today announced that Mentor’s design-for-manufacturing (DFM) and design-for-test (DFT) tools have been incorporated into TSMC Reference Flow 8.0. The new Reference Flow 8.0 features Mentor tools for critical area analysis and reduction, chemical-mechanical polishing (CMP) analysis and layer planarity control using smart fill algorithms, litho-friendly design, process variability aware analysis, and DFT flows based on Mentor Graphics Calibre® and TestKompress® solutions. Other Reference Flow 8.0 advances include statistical timing analysis for intra-die variation, automated DFM hot-spot fixing and new dynamic low-power design methodologies. “Mentor is pleased to have the opportunity to again demonstrate the production worthiness of our DFM and DFT solutions at the world’s premier dedicated semiconductor foundry,” said Joe Sawicki, vice president and general manager, Design to Silicon Division, Mentor Graphics. “Our continued collaboration with TSMC will help designers address the challenges of nanometer semiconductor design and manufacturing.” “We believe that Mentor Graphics’ DFM tools will further expand the confidence of designers who have been using Calibre for physical verification signoff,” said Kuo Wu, deputy director of design services marketing at TSMC. “Mentor Graphics DFM tools are interoperable with the design tools in Reference Flow 8.0, enabling them to fit easily into our customers’ flows.” About the Mentor Graphics DFM Platform Calibre YieldAnalyzer performs critical area analysis (CAA) on all base and interconnect layers to identify areas of a layout with excess vulnerability to random particle defects, such as shorts and opens, due to close spacing of layout features. YieldAnalyzer provides guidance to help the designer quickly locate hot spots and determine what layout changes will result in the greatest yield improvement. This data is forward annotated to P&R tools like Sierra Olympus-SOC automatically reducing the critical area while ensuring that correct timing is preserved. Calibre YieldEnhancer™ automatically specifies a variety of interconnect and base layer enhancements such as via doubling, via enclosure expansion and general edge moving to improve yield. Modifications are fully back annotated to GDSII, OASIS™, LEF/DEF, OpenAccess™ and Milky Way™ design databases. The Calibre CMP solution is integrated with TSMC’s Vertical CMP (VCMP) simulator, enabling the designer to model the CMP process and automatically add fill to the layout based on layout density, gradient and magnitude assessments. This intelligent “model-based fill” approach provides optimum planarity improvement to reduce bridging due to dishing and thickness variations, while minimizing added parasitic capacitance and its impact on timing. Calibre extraction tools, xRC and xL, also integrate with VCMP to create a comprehensive 3D circuit model with device and interconnect parameters that more closely match silicon results. The results can drive extremely accurate simulations using Mentor’s ADiT™ or other leading circuit simulators supported by Calibre’s back annotation facilities. DFT capabilities based on Mentor Graphics TestKompress, MBISTArchitect™, and YieldAssist™ products, which have been part of TSMC’s reference flow since version 6, continue to include both logic and memory testing. New facilities in Reference Flow 8.0 include power reporting during ATPG (automatic test program generation) for addressing test-specific power issues, and timing-aware ATPG features for targeting small delay defects. About Mentor Graphics About TSMC
Mentor Graphics, Calibre, and TestKompress are registered trademarks and Calibre LFD, Calibre xRC, ADiT, Yield Enhancer, YieldAnalyzer, YieldAssist and MBISTArchitect are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners. For more information, please contact: Laurie Brunner Sonia Harrison
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