Digital IC Design

Innovative Technologies for Fast & High-Quality Design Closure at Advanced Process Nodes

Mentor Graphics IC implementation solutions, Olympus-SoC™ and Calibre® InRoute, deliver innovative technologies to solve the power, performance, capacity, time-to-market, and variability challenges encountered at the leading-edge process nodes.

Olympus-SoC Overview

Olympus-SoC Overview

Technology Overview The Olympus-SoC™ Design for Variability IC implementation solution is purpose-built to address the performance, capacity, time-to-market, and variability challenges at advanced nodes. With full support...

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The Olympus-SoC netlist-to-GDSII system performs variation- and power-aware rapid feasibility, including placement, advanced clock tree synthesis, and optimization for all mode/corner scenarios concurrently.

Calibre InRoute Overview

Calibre InRoute Overview

Technology Overview Mentor Graphics developed Calibre InRoute to support manufacturing closure for advanced node designs by bringing Calibre signoff capabilities into the place and route environment.

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The Calibre InRoute design and verification platform includes all Olympus-SoC capabilities, plus true Calibre DRC and DFM signoff within the place and route environment.

Benefits

  • Boost IC performance with advanced multi-corner, multi-mode (MCMM) optimization
  • Reduce power consumption in clock trees with MCMM clock tree synthesis
  • Improve yield with DFM-aware routing to address lithography issues in a timing context during implementation
  • Perform Calibre physical signoff analysis and automated fixing of DRC and DFM issues for faster and more reliable manufacturing closure.
  • Speed time-to-market with fewer design iterations, scalable multi-threading, and sign-off quality closure
  • Load and process designs of 400M gates or more with the industry's highest-capacity data structure
  • Reduce costs through high yields and fast time-to-market

Digital IC Design Products

  • Calibre InRoute

    Calibre InRoute enables designers to achieve signoff-quality manufacturing closure during physical design within the Olympus-SoC place and route system.

  • Olympus-SoC

    The Olympus-SoC™ physical implementation platform meets the highest demands of IC designs at advanced nodes.

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Executive Brief: Meeting the Critical Challenges of IC Implementation

Executive Brief: Meeting the Critical Challenges of IC Implementation

On-demand Web Seminar

At the 2008 Design Automation Conference in June, Joseph Sawicki, vice president and general manager of the Design to Silicon Division, laid out Mentor’s strategy to help customers with the challenges... View Video