Digital IC Design
Innovative Technologies for Fast & High-Quality Design Closure at Advanced Process Nodes
Mentor Graphics IC implementation solutions, Olympus-SoC™ and Calibre® InRoute, deliver innovative technologies to solve the power, performance, capacity, time-to-market, and variability challenges encountered at the leading-edge process nodes.
Pravin Madhani at DAC 2012
Technology Overview Interview with Mentor Graphics' Pravin Madhani at DAC 2012.
The Olympus-SoC netlist-to-GDSII system performs variation- and power-aware rapid feasibility, including placement, advanced clock tree synthesis, and optimization for all mode/corner scenarios concurrently.
Calibre InRoute Overview
Technology Overview Mentor Graphics developed Calibre InRoute to support manufacturing closure for advanced node designs by bringing Calibre signoff capabilities into the place and route environment.
The Calibre InRoute design and verification platform includes all Olympus-SoC capabilities, plus true Calibre DRC and DFM signoff within the place and route environment.
- Boost IC performance with advanced multi-corner, multi-mode (MCMM) optimization
- Reduce power consumption in clock trees with MCMM clock tree synthesis
- Improve yield with DFM-aware routing to address lithography issues in a timing context during implementation
- Perform Calibre physical signoff analysis and automated fixing of DRC and DFM issues for faster and more reliable manufacturing closure.
- Speed time-to-market with fewer design iterations, scalable multi-threading, and sign-off quality closure
- Load and process designs of 400M gates or more with the industry's highest-capacity data structure
- Reduce costs through high yields and fast time-to-market