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Place and route for advanced node designs

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The Olympus-SoC™ Netlist-to-GDSII system comprehensively addresses the performance, capacity, time-to-market, power, and variability challenges encountered at the leading-edge process nodes. It is a complete physical design implementation tool for the complex multi-patterning and FinFET requirements of advanced process technologies.

Olympus-SoC provides the highest capacity in the industry, with a very compact and scalable database capable of handling designs with hundreds of millions of instances. Its low-power suite enables both leakage and dynamic power reduction throughout the flow, and power-aware clock tree synthesis.

“We are pleased with the Olympus-SoC integrated platform’s ability to deliver a 20 nm place and route solution with high quality of results, which we recently demonstrated on a 20 nm test chip tapeout.”

Philippe Magarshack, Group Vice President, STMicroelectronics Technology Research and Development

“We have used Olympus-SoC on multiple GPU tapeouts and are very impressed with the overall quality of results and design schedule savings.”

Sameer Halepete, Vice President, ASIC Engineering, NVIDIA Corporation

“Our design methodology is based on a multi-level hierarchical approach in order to optimize performance, to take advantage of a modular and repetitive design and to overcome implementation complexity. The fact that Mentor’s platforms work together seamlessly is a definite productivity enhancer, but just as critical, each tool needs to have the features, speed, accuracy and capacity to handle designs at this scale.”

Joël Monnier, CEO, KALRAY Corporation

“The Olympus-SoC system is already part of our Reference Design Flow (RDF) kit, which is being used for many advanced designs to rapidly close complex multi-corner multi-mode (MCMM) design issues. Now the new fully-parallelized Olympus-SoC timer will give us much faster turnaround for those design closures by taking full advantage of the most advanced multicore processors.”

Shoji Ichino, General Manager, Technology Development Division, Fujitsu Microelectronics Limited

Best Performance and Predictability

Best Performance and Predictability

Olympus-SoC avoids unpredictability in sign-off ECO loops, eliminates performance-killing pessimism, and speeds the time-to-tapeout by considering all scenarios concurrently, from floorplanning to GDSIII-out.

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Automatic macro placement

Highest Capacity and Scalability

Olympus-SoC can easily handle 100+ million gate designs because it has the industry’s highest-capacity, smallest-footprint, ultra-compact database. Its flexible architecture enables flat, hierarchical, or pseudo-flat flows with a dataflow, graph-driven macro placement engine.

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Fastest Turn-around Time

Olympus-SoC helps you achieve design closure on large complex designs in a fraction of the time required for existing design flows. With Olympus-SoC, you can speed design closure time by a factor of 2-3X, and reduce power by up to 30% over traditional tools.

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Lowest Design Cost

Lowest Design Cost

Olympus-SoC features a scalable and flexible routing architecture that integrates the global, track, and detailed routing engines best suited to handle multi-patterning and FinFET requirements of advanced nodes.

The router supports all the complex DRC, DFM, and MP rules for all the leading foundries. The Olympus-SoC router is able to address the increased number and complexity of DRC rules with fast runtimes and no loss in accuracy.

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