Olympus-SoC

Design for Variability refers to analysis and implementation of a physical design taking into account multiple design contexts or modes, as well as timing variations due to device and interconnect scaling. Traditional techniques, like merging constraints over design modes or merging process corners, result in significant loss of accuracy, which impacts design yield, timing closure and time-to-market at advanced process nodes. Often, designers are forced to iterate unpredictably in multiple sign-off ECO loops, or add pessimistic margins resulting in designs with larger area and power dissipation, and lower yields.

Olympus-SoC eliminates this shortcoming with native MCMM optimization across any number of modes, corners and power states, concurrently. During detailed routing, Design-for-Manufacturing (DFM) analysis engines for critical area, CMP (metal fill), and lithography work together with timing, power and die size analysis engines to produce a fully-optimized physical design across all modes and corners.

Multi-CPU ECO routing is integrated with post-route optimization to achieve rapid timing closure. Routing enhancements are done without affecting the overall timing performance or introducing OCV-related hold violations. Unique routing technology enables live interaction between route-based variability optimization and detailed routing to ensure that variability and routing engines are constantly in-sync with all changes made to the design. All engines are linked to the embedded variation-aware timing engine to achieve timing closure across all modes and corners during routing.

At 65nm process nodes and below, there is increasing distortion in the printed patterns vis-à-vis the intended structures in the layout database. This problem manifests itself in the form of manufacturing faults such as bridging, pinching and via failures. Although OPC helps address this challenge, at 65nm and below, the number of issues becomes very large, and trying to fix them all in manufacturing becomes intractable. Further, litho-related layout modifications done in isolation of design metrics, such as timing, leakage, planarity and other parameters, can lead to performance degradation and timing-related chip failures.

Olympus-SoC includes a multi-CPU-enabled DRC engine that evaluates complex shape-based DRCs during routing to produce inherently more litho-friendly designs by making changes to the layout to correct lithography hot-spots. A hybrid analysis approach provides the speed of gridded routers with the accuracy of gridless approaches.

With the rapid growth in design sizes, designers are moving to larger block sizes in hierarchical flows, and are using flat physical design flows to reduce die-area and cost. Chip Assembly flows are also gaining traction to achieve top-level design closure over multiple blocks. Designers need tools physical implementation tools with very high capacity to address this variety of design styles, but current-generation implementation systems were not architected to handle these inherent challenges at 65nm and beyond.

Olympus-SoC was purpose-built with a highly-efficient and scalable architecture that can accommodate an arbitrary number of timing graphs to represent each variation scenario (and its related set of design corners) concurrently. Designers can optimize designs for multiple operational modes, as well as variations in lithography and other manufacturing processes windows, in a comprehensive and holistic fashion. Olympus-SoC has extremely concise data structures, small memory footprint, fully multi-threaded analysis engines, and the industry’s only parallelized timing and optimization engine. As a result, Olympus-SoC can handle the most complex SoC designs with 100+ million gates, in either flat or hierarchical mode, with unmatched turnaround times and without forcing design segmentation.