Place and route for advanced node designs
The Olympus-SoC™ physical implementation platform meets the challenges of manufacturability and low-power for IC designs at advanced nodes. Olympus-SoC delivers high quality layouts, fast turnaround, and rapid closure.
Macro Placement in Olympus-SoC
Product Demo This video shows the automatic macro placment capabilities in the Olympus-SoC place and route system. It also shows examples of the improved design metrics the Olympus-SoC macro placer achieves.
Olympus-SoC enables manufacturing closure by addressing lithographic distortions seen at nanometer nodes. These distortions degrade performance and signal integrity, and lead to manufacturing faults such as bridging, pinching and via failures resulting in lower yield and reliability.
In the past, these distortions could be corrected during mask preparation. Today, post-layout modifications are no longer sufficient and all foundries require designers to perform DFM checks.
The Olympus-SoC lithography-driven router addresses the complex lithograhy effects during place and route with integrated critical area analysis (CAA), CMP, and OPC models. Because the router is DFM-aware, it produces an inherently litho-friendly layout with MCMM optimization and high-quality routing, ensuring robust, full-process-window manufacturability.
Olympus-SoC directly accesses all Calibre signoff engines through the Calibre InRoute interactive design and manufacturing closure tool, ensuring that all manufacturability issues are addressed without introducing new issues, or degrading design performance.
Olympus-SoC with Calibre InRoute offers:
- Automated, intelligent prevention of DRC/DFM issues
- True signoff analysis
- Automatic fixing of DRC and DFM violations during physical design
Olympus-SoC comprehensively handles the requirements of low-power design. It ensures optimization of the overall solution without excessive iterations, enabling engineers to rapidly deliver fully-optimized, power-efficient designs.
With a true MCMM capability, Olympus-SoC provides seamless concurrent optimization for both power and timing, covering all operating modes and process corners through all stages of the flow. It fully supports the Unified Power Format (UPF) from netlist-to-GDSII, and can describe design intent through power state definition tables. It also supposed dynamic voltage and frequency scaling (DVFS) to handle varying supply voltages and clock frequencies.
To reduce dynamic power, Olympus-SoC provides automatic power-aware clock tree synthesis (CTS) with smart clock gate placement, slew shaping, register clumping and concurrent MCMM optimization, ensuring a balanced clock tree with the minimum number of clock buffers.
Olympus-SoC completely automates multi-supply voltage design flows with automatic power grid routing for multiple voltage supplies, and manages auto placement and routing of special cells such as level shifters, isolation cells, and MTCMOS switches. Olympus-SoC also provides:
- Concurrent multi-Vt optimization
- Power gating
- Retention flop synthesis
- Support for gas station methodology
- Power-aware buffering and sizing
Productivity and Big Data
Olympus-SoC helps you achieve design closure on large complex designs in a fraction of the time required for existing design flows. With Olympus-SoC, you can speed design closure time by a factor of 2-3X, and reduce power by up to 30% over traditional tools.
Olympus-SoC can handle more than 100 million gate designs because it has the industry’s highest-capacity, smallest-footprint, ultra-compact database. Its flexible architecture enables flat, hierarchical, or pseudo-flat flows with a dataflow, graph-driven macro placement engine.
Olympus-SoC also includes physical synthesis technology, which delivers highly optimized results for multimillion-gate flat designs in a single overnight run.
Sign-off quality timing, extraction, and delay calculation are native to the Olympus-SoC kernel. Fully-multithreaded analysis engines and a fully-parallelized timing and optimization engine reduce run times by efficiently using the latest platforms, providing a significant speedup.
Variability and Performance
Olympus-SoC helps you manage process variability at advanced nodes by taking into account multiple design modes, process corners, power states, and timing variations. Traditional techniques, like merging constraints over design modes or merging process corners, result in significant loss of accuracy, which impacts design yield, timing closure and time-to-market.
Olympus-SoC improves on traditional techniques for managing variability with native concurrently MCMM optimization across any number of modes, corners, and power states. The patented “virtual timing graph” architecture enables the database to handle any number of timing views of the design with minimal impact on runtimes and memory requirements.
Multi-CPU ECO routing is integrated with post-route optimization in Olympus-SoC to achieve rapid timing closure. Routing enhancements are done without affecting the overall timing performance or introducing OCV-related hold violations.
The unique routing technology of Olympus-SoC enables live interaction between route-based variability optimization and detailed routing to ensure that variability and routing engines are constantly in-sync with all changes made to the design. All engines are linked to the embedded variation-aware timing engine to achieve timing closure across all modes and corners during routing.
Features and Benefits
- Concurrent optimization for power and timing with the native multi-corner, multi-mode (MCMM) architecture
- Automated support for all low-power design techniques
- Reduced clock-related dynamic power through advanced MCMM clock tree synthesis
- DFM optimizations, including critical area analysis, litho, and planarity
- Native invocation of Calibre signoff engines through Calibre InRoute
- Excellent scaling on multicore and multi-CPU computing platforms
- Unmatched tool capacity of 100 million+ gates
- Full support for flat, hierarchical, and pseudo-flat flows
- Data-flow driven macro placement engine
Contact Mentor Graphics
- Olympus-SoC Info Request or call toll free: 1-800-547-3000
“Not only did Olympus-SoC make it easier and faster to close the design, but we also got much better quality of results...&rdquo”
“Calibre InRoute has successfully corrected the DRC violations caused by several complex IPs, whose 'abstract' views did not fully match the underlying layout. Besides catching manufacturability issues early in the design flow, Calibre InRoute allows us to automatically find and repair violations without leaving the Olympus cockpit. This saves engineering time and ensures that no new violations will be created by the fixes.”
“We are pleased with the Olympus-SoC integrated platform’s ability to deliver a 20 nm place and route solution with high quality of results, which we recently demonstrated on a 20 nm test chip tapeout.”
“The Olympus-SoC system is already part of our Reference Design Flow (RDF) kit, which is being used for many advanced designs to rapidly close complex multi-corner multi-mode (MCMM) design issues. Now the new fully-parallelized Olympus-SoC timer will give us much faster turnaround for those design closures by taking full advantage of the most advanced multicore processors.”