Olympus-SoC

Solving 65 nm and 45 nm Design Challenges

The Olympus-SoC™ IC implementation solution is purpose-built to address the performance, capacity, time-to-market, and variability challenges at advanced nodes. With full support for low-power design styles, signoff-quality timing analysis and optimization, and DFM-aware routing, Olympus-SoC delivers the highest quality layouts with fast turnaround and rapid closure.

Advanced Support for Low Power

The Olympus-SoC low power platform comprehensively handles the requirements of low-power design. It ensures optimization of the overall solution without excessive iterations, enabling engineers to rapidly deliver fully-optimized, power-efficient designs.

Olympus-SoC provides seamless concurrent optimization for both power and timing, covering all operating modes and process corners through all stages of the flow. It completely automates multi-supply-voltage design flows with automatic power grid routing for multiple voltage supplies, support for Dynamic Voltage and Frequency Scaling (DVFS) to handle varying supply voltages and clock frequencies, and auto placement and routing of special cells such as level shifters, isolation cells, and MTCMOS switches. Olympus-SoC also provides concurrent multi-Vt optimization, power gating, retention flop synthesis, support for gas station methodology, and power-aware buffering and sizing.

To reduce dynamic power, Olympus-SoC provides automatic power-aware clock tree synthesis (CTS) with smart clock gate placement, slew shaping, register clumping and concurrent MCMM optimization, ensuring a balanced clock tree with the minimum number of clock buffers.

Olympus-SoC supports the Unified Power Format (UPF) throughout the netlist-to-GDSII flow, including the ability to describe design intent through power state definition tables. The ability to process 100 million + gates in flat or hierarchical modes provides better, faster chip assembly and full-chip power optimization.

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New Discontinuity @ 65nm

Technology Overview

The semiconductor industry is in a period of unprecedented change. View more about the new discontinuity @ 65nm. View Video

Best Quality-of-Results in Physical Design

Olympus-SoC delivers concurrent optimization of timing, signal integrity, die size, leakage and dynamic power across all design and process corners throughout the design flow. It automatically analyzes manufacturing variability issues and drives optimizations throughout the implementation, starting with floor planning, and continuing through feasibility, placement, optimization, clock tree synthesis, and routing.

The next-generation routing architecture incorporates variation-aware timing optimization and litho-modeling to address DFM and OPC effects early in the design cycle. Early DFM analysis allows Olympus-SoC to provide a high correlation with industry-standard timing and physical verification sign-off tools.

Shorter Turnarounds and Faster Design Closure

Olympus-SoC’s ultra-compact database provides the industry's highest capacity and smallest memory footprint, allowing it to handle 100 million + gate designs. The patented “virtual timing graph” architecture enables Olympus-SoC to handle any number of timing views of the design with minimal impact on runtimes and memory requirements. Patent-pending physical synthesis technology gives highly-optimized results for multi-million gate flat designs in a single overnight run. New advances in performance bottleneck detection and analytical optimization address the complex challenge of constraint validation for "dirty" design data, providing robust optimization in the presence of ill-formed constraints.

Sign-off quality timing, extraction, and delay calculation are native to the Olympus-SoC kernel. Fully-multithreaded analysis engines and the industry’s only fully-parallelized timing and optimization engine slash run times by efficiently using the latest platforms, providing a 7x speedup on an 8-CPU machine. The combination of these features allows Mentor customers to achieve design closure on large complex designs in a fraction of the time required for existing design flows. Olympus-SoC customers are experiencing 2-3X faster design closure times in addition to an additional 30% power savings versus traditional tools.

Highlights

Features and Benefits

  • Unique native MCMM architecture provides seamless concurrent optimization for both power and timing, covering all operating modes and corners through all stages of the flow.
  • Full support for all low power design techniques with automated placement and routing of power-specific cells in multi-Vdd, multi-VT and DVFS designs.
  • Advanced MCMM CTS to reduce clock-related dynamic power.
  • Full support for UPF.
  • Optimizes physical designs for DFM issues, such as CAA, litho and CMP, across multiple design contexts and multiple manufacturing process windows.
  • High performance on designs with over 100 million gates in flat mode, or any number of design hierarchy levels.
  • Fully-parallelized architecture scales efficiently on multicore and multi-CPU platforms.
  • Better QoR and faster design closure for the largest and most complex low power SoC designs.
  • MCMM optimization delivers higher performance and low power.
  • Fewer iterations and less manual analysis required to reach design closure.
  • Delivers more robust designs that are less sensitive to manufacturing variability.
  • Fast turnaround even on extremely large designs.
  • No need to segment designs due to tool capacity limitations.
  • Excellent scaling on multicore and multi-CPU computing platforms

Comprehensive Low Power Design Capabilities

The Olympus-SoC low power platform comprehensively handles the requirements of low-power design, while ensuring optimization of the overall solution without excessive design iterations, enabling engineers to rapidly deliver fully-optimized, power-efficient designs:

  • Seamless concurrent optimization for both power and timing, covering all operating modes and corners through all stages of the flow.
  • Completely automated multi-voltage flow with automatic power grid routing for multiple voltage supplies, support for Dynamic Voltage and Frequency Scaling (DVFS), and automatic placing and routing of special cells such as level shifters, isolation cells, and MTCMOS switches.
  • Concurrent Multi-Vt optimization, power gating, retention flop synthesis, gas station methodology, and power-aware buffering and sizing.
  • Power aware clock tree synthesis (CTS) with smart clock gate placement, slew shaping, register clumping and concurrent MCMM optimization that ensures a balanced clock tree with the minimum number of clock buffers.
  • Unified Power Format (UPF)-based Netlist-to-GDSII flow including support for power state definition tables.
  • Ability to process 100 million + gates in flat mode allows efficient full-chip power optimization.

Datasheets

Technical Resources

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How NXP Enabled Fast and Predictable Design Closure

Testimonial

NXP engineer Andy Appleby discusses the challenges of designing their digital TV chip, the PNX8550, and how Olympus-SoC enabled fast and predictable design closure. View Video

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Customer Quotes

“We build some of the world’s largest and highest performance ICs and it’s crucial for us to maintain design schedules in the face of increasing IC complexity. We have used Olympus-SoC on multiple GPU tapeouts and are very impressed with the overall quality of results and design schedule savings.”

Sameer Halepete, vice president of ASIC Engineering at NVIDIA

“We worked with Mentor Graphics to qualify Olympus-SoC for our 40nm process. All our requirements were met and we expect designers to benefit as they we expect designers to benefit as they move to TSMC's most advanced production process.”

S.T. Juang, Senior Director of Design Infrastructure Marketing, TSMC

“We used Olympus-SoC to tape out an advanced set-top box chip containing 12 million gates and manufactured using an 80nm process. We are extremely pleased with the Olympus-SoC product's ability to deliver this first-pass functional silicon, and we are impressed with the overall quality of results including design rule check (DRC) clean routing, multi-corner-multi-mode timing closure, and fast runtimes for large capacity chips.”

Thierry Bauchon, R&D Director, Home Entertainment & Displays Group, STMicroelectronics

“We used the new timing and optimization technology in Olympus-SoC for the extremely complicated EMMA design, which has over 30 million gates, four modes and four corners, a 200MHz main clock, and over 150 derived clocks. We are very impressed with Olympus-SoC’s performance improvements, which provided almost a factor of four reduction in our design closure time.”

Mr. Masao Hirasawa, General Manager, Digital Consumer LSI Division, NEC Electronics Corporation

Olympus-SoC Solution

Next Generation Netlist-to-GDSII System Comprehensively Addresses Variations in Design Modes, Process Corners, and Lithography.

With early 65nm chips heading towards production and 45nm test chip trials under-way, three critical physical design tool needs have emerged: lithography-aware physical implementation; variation-based timing closure; and capacity to handle extremely high gate counts.

Olympus-SOC Solution:DFM to Address Design Variability

Design for Variability refers to analysis and implementation of a physical design taking into account multiple design contexts or modes, as well as timing variations due to device and interconnect scaling. Traditional techniques, like merging constraints over design modes or merging process corners, result in significant loss of accuracy, which impacts design yield, timing closure and time-to-market at advanced process nodes. Often, designers are forced to iterate unpredictably in multiple sign-off ECO loops, or add pessimistic margins resulting in designs with larger area and power dissipation, and lower yields.

Olympus-SoC eliminates this shortcoming with native MCMM optimization across any number of modes, corners and power states, concurrently. During detailed routing, Design-for-Manufacturing (DFM) analysis engines for critical area, CMP (metal fill), and lithography work together with timing, power and die size analysis engines to produce a fully-optimized physical design across all modes and corners.

Multi-CPU ECO routing is integrated with post-route optimization to achieve rapid timing closure. Routing enhancements are done without affecting the overall timing performance or introducing OCV-related hold violations. Unique routing technology enables live interaction between route-based variability optimization and detailed routing to ensure that variability and routing engines are constantly in-sync with all changes made to the design. All engines are linked to the embedded variation-aware timing engine to achieve timing closure across all modes and corners during routing.

Litho-aware Routing

At 65nm process nodes and below, there is increasing distortion in the printed patterns vis-à-vis the intended structures in the layout database. This problem manifests itself in the form of manufacturing faults such as bridging, pinching and via failures. Although OPC helps address this challenge, at 65nm and below, the number of issues becomes very large, and trying to fix them all in manufacturing becomes intractable. Further, litho-related layout modifications done in isolation of design metrics, such as timing, leakage, planarity and other parameters, can lead to performance degradation and timing-related chip failures.

Olympus-SoC includes a multi-CPU-enabled DRC engine that evaluates complex shape-based DRCs during routing to produce inherently more litho-friendly designs by making changes to the layout to correct lithography hot-spots. A hybrid analysis approach provides the speed of gridded routers with the accuracy of gridless approaches.

High Capacity and Scalability

With the rapid growth in design sizes, designers are moving to larger block sizes in hierarchical flows, and are using flat physical design flows to reduce die-area and cost. Chip Assembly flows are also gaining traction to achieve top-level design closure over multiple blocks. Designers need tools physical implementation tools with very high capacity to address this variety of design styles, but current-generation implementation systems were not architected to handle these inherent challenges at 65nm and beyond.

Olympus-SoC was purpose-built with a highly-efficient and scalable architecture that can accommodate an arbitrary number of timing graphs to represent each variation scenario (and its related set of design corners) concurrently. Designers can optimize designs for multiple operational modes, as well as variations in lithography and other manufacturing processes windows, in a comprehensive and holistic fashion. Olympus-SoC has extremely concise data structures, small memory footprint, fully multi-threaded analysis engines, and the industry’s only parallelized timing and optimization engine. As a result, Olympus-SoC can handle the most complex SoC designs with 100+ million gates, in either flat or hierarchical mode, with unmatched turnaround times and without forcing design segmentation.