Place and route for advanced node designs
The Olympus-SoC™ physical implementation platform meets the challenges of manufacturability and low-power for IC designs at advanced nodes. Olympus-SoC delivers high quality layouts, fast turnaround, and rapid closure.
“Not only did Olympus-SoC make it easier and faster to close the design, but we also got much better quality of results...”
Kazuhisa Miyamoto Senior Director, MONOZUKURI Innovation Group Hardware MONOZUKURI Division Information & Telecommunication Systems Group
“Calibre InRoute has successfully corrected the DRC violations caused by several complex IPs, whose 'abstract' views did not fully match the underlying layout. Besides catching manufacturability issues early in the design flow, Calibre InRoute allows us to automatically find and repair violations without leaving the Olympus cockpit. This saves engineering time and ensures that no new violations will be created by the fixes.”
Philippe Magarshack Group Vice President STMicroelectronics Technology Research and Development
“We are pleased with the Olympus-SoC integrated platform’s ability to deliver a 20 nm place and route solution with high quality of results, which we recently demonstrated on a 20 nm test chip tapeout.”
Philippe Magarshack Group Vice President STMicroelectronics Technology Research and Development
“The Olympus-SoC system is already part of our Reference Design Flow (RDF) kit, which is being used for many advanced designs to rapidly close complex multi-corner multi-mode (MCMM) design issues. Now the new fully-parallelized Olympus-SoC timer will give us much faster turnaround for those design closures by taking full advantage of the most advanced multicore processors.”
Shoji Ichino General Manager Technology Development Division Fujitsu Microelectronics Limited
Advanced Node Support
Olympus-SoC features a scalable and flexible routing architecture that integrates the global, track, and detailed routing engines best suited to handle multi-patterning (MP) and FinFET requirements of advanced nodes. The router supports all the complex DRC, DFM, and MP rules for all the leading foundries.
The Olympus-SoC router is able to address the increased number and complexity of DRC rules with fast runtimes and no loss in accuracy. The unified Global Router based congestion modeling ensures excellent correlation in all stages of the design flow. The routing engine incorporates signoff-quality, variation-aware timing and optimization engine for SI- and timing-driven routing.
The router supports both gridded and non-gridded models and the use of a universal connectivity model for a friendly ECO flow. It also supports sophisticated non-default rules (NDRs) and all the DFM requirements for advanced nodes including recommended rules, pattern matching, redundant vias, wire spreading/widening, and timing-aware smart metal and via fill. Key features for supporting advanced node designs include:
- Comprehensive multi patterning and FinFET support
- Native coloring, verification and conflict resolution
- DRC, double/multi patterning, and DFM rule support for all leading foundries
- Intelligent conflict double/multi patterning
- Resolution engine
- Pattern matching and recommended rules support
- Variation-aware timing and SI driven routing
To tackle the challenges of growing design sizes, such as runtime and tool capacity, Olympus-SoC provides multiple design planning options including flat, hierarchical and pseudo flat floorplanning technologies. Hierarchical floorplanning supports both channel-based and channel-less (abutted) flows and offers unique technologies such as timing- and congestion-aware pin placement and feed-through insertion. The data flow graph driven automatic macro placement for both top and block level (AMP) ensures the best QoR by facilitating design space exploration with multiple parallel recipes, which significantly reduces the number of macro placement iterations. Olympus-SoC offers the highest tool capacity, compact memory footprint, and intuitive, easy to use GUI. Key features for supporting design planning include:
- Design planning including flat, hierarchical, and pseudo flat floorplanning
- Support for both channel-less and channel-based flows
- Timing and congestion aware pin placement and feed-through insertion
- Data flow graph driven automatic macro placement
- Timing-driven placement engine for optimal QoR
- Powerful and efficient GUI
Leading-edge designs need to be analyzed and optimized for various design contexts and timing variations due to device/interconnect scaling. Using approximations, like constraint merging or adding margins, results in loss of accuracy that impacts design performance, and time-to-market. With Olympus-SoC, you can avoid unpredictability in sign-off ECO loops, eliminate performance-killing pessimism, and speed the time-to-tapeout by considering all the scenarios concurrently, from floorplanning to GDSII-out.
Olympus-SoC’s patented and tape-out proven multi-corner–multi-mode (MCMM) architecture drives the router and optimization engines to automatically achieve best timing and SI across all modes and corners concurrently. The patented “virtual timing graph” architecture enables the database to handle any number of timing views of the design with minimal impact on runtimes and memory requirements. Additional technologies such as 3D opportunistic shielding of clock nets, CTS-based timing optimization and advanced trap placement help push the performance envelope. Key features that enable the highest performance designs include:
- True and concurrent MCMM optimization during all design steps
- Best-in-class MCMM-based CTS
- On-chip variation (OCV) driven CTS and opportunistic 3D clock shielding
- Resistance-aware concurrent cell and wire optimization
- Extremely fast and accurate, on-the-fly parasitic extraction
- Sign-off quality timing analysis and optimization
Low Power Platform
Olympus-SoC provides seamless concurrent optimization for both power and timing, covering all operating modes and process corners through all stages of the flow. Olympus-SoC supports the Unified Power Format (UPF) throughout the netlist-to-GDSII flow, including the ability to describe design intent through power state definition tables.
Olympus-SoC automates multi-supply-voltage design flows with automatic power grid routing for multiple voltage supplies, support for dynamic voltage and frequency scaling (DVFS) to handle varying supply voltages and clock frequencies, and auto placement and routing of special cells such as level shifters, isolation cells, and MTCMOS switches.
It also provides concurrent multi-Vt optimization, power gating, retention flop synthesis, support for gas station methodology, and power-aware buffering and sizing. Power-aware CTS minimizes power in the clock network with techniques like smart clock gate placement, slew shaping, clock gate cloning/de-cloning, register clumping and concurrent MCMM optimization, all of which ensure a balanced clock tree with optimal power. Key features of the Olympus-SoC low power platform include:
- Concurrent multi-Vt optimization
- Power gating
- Support for gas station methodology
- Power-aware buffering and sizing
- UPF 2.0 (IEEE 1801) based multi voltage flow
- Power state table (PST) based advanced buffering
- Support for level shifters, isolation cells, and retention registers
- Distributed and ring style multi-threshold (MTCMOS) switch cell insertion
- Hierarchical UPF support
- Power aware CTS featuring cloning, restructuring, and slew shaping
- Concurrent power and timing optimization for all corner/mode/power scenarios
Dynamic Area Recovery
At advanced nodes, the introduction of multi patterning and the FinFET transistor have a significant impact on design utilization and area due to complex spacing requirements. It is critical to accurately predict intra-cell congestion and recover area throughout the design flow.
Olympus-SoC reduces area with technologies like the unified global router-based congestion modeling, intelligent white space management, smart MP fixing for nested and interdependent cycles, Fin grid-aware placement, Vt- and implant-aware spacing and concurrent SI and MP fixing.
Other area reduction technologies used throughout the flow include proprietary density management, dynamic area recovery, and congestion mitigation though clock tree synthesis (CTS) and post-CTS optimization. Key features for area reduction include:
- Unified global router based congestion modeling
- Channel-less floorplanning flow
- Intelligent white space management
- Precision DP fixing for minimal perturbation
- Dynamic area recovery throughout the flow
- Proprietary density management
Productivity and Capacity
Olympus-SoC helps you achieve design closure on large complex designs in a fraction of the time required for existing design flows. With Olympus-SoC, you can speed design closure time by a factor of 2-3X, and reduce power by up to 30% over traditional tools.
Olympus-SoC can handle more than 100 million gate designs because it has the industry’s highest-capacity, smallest-footprint, ultra-compact database. Its flexible architecture enables flat, hierarchical, or pseudo-flat flows with a dataflow, graph-driven macro placement engine. Olympus-SoC also includes physical synthesis technology, which delivers highly optimized results for multimillion-gate flat designs in a single overnight run.
Sign-off quality timing, extraction, and delay calculation are native to the Olympus-SoC kernel. Fully-multithreaded analysis engines and a fully-parallelized timing and optimization engine reduce run times by efficiently using the latest platforms, providing a significant speedup. Key features supporting productivity and capacity include:
- Distributed and multithreaded analysis and optimization
- Signoff physical verification during implementation with Calibre InRoute
- Minimal ECO iterations through MCMM optimization
- Signoff quality built-in timing and extraction engines
- Industry’s first multi-threaded timing engine
- Compact database and flexible architecture
- Ability to handle 100+ million instance designs
- Flexible abstraction capabilities including SI-ILM, HTP, and black boxes
- Unique synchronized optimization at the top-level design
- Advanced memory reduction technologies
The Olympus-SoC lithography-driven router addresses the complex lithograhy effects during place and route with integrated critical area analysis (CAA), CMP, and OPC models. Because the router is DFM-aware, it produces an inherently litho-friendly layout with MCMM optimization and high-quality routing, ensuring robust, full-process-window manufacturability.
Olympus-SoC uses an “open router” architecture that allows it to natively invoke of all the signoff Calibre engines during implementation through the Calibre InRoute advanced design and manufacturing closure platform. Invoking Calibre facilities directly within the Olympus-SoC environment provides automated, intelligent prevention of DRC/DFM/MP issues, true signoff analysis, and automatic fixing of DRC/DFM/MP violations during the physical design process. Calibre InRoute ensures that all manufacturability issues are addressed without introducing new ones, and without degrading the performance of the design. The open router architecture also eliminates the need for any serial data transfers, as all the engines use the same hosted data model. Key features of Olympus-SoC with Calibre InRoute include:
- Automated, intelligent prevention of DRC/DFM issues
- True signoff analysis
- Automatic fixing of DRC and DFM violations during physical design