Fast and high-quality physical RTL synthesis for advanced node designs
The RealTime Designer™ physical RTL synthesis solution addresses the need for higher capacity, faster runtimes, improved QoR, and physical awareness by optimizing at a higher level of abstraction and using integrated floorplanning and placement capabilities. RealTime Designer provides better quality of results by enabling physical accuracy, floorplanning, and fast optimization iterations to get to design closure on time.
RealTime Designer takes an entire chip design from RTL all the way to placed gates/macros in a single pass. It reads the entire design, then assigns high-level modules in the RTL to regions then partitions the RTL into placeable pieces. Hard macros are provisionally placed, and any physical hierarchy is honored. RealTime Designer uses patented technology to access a fully detailed netlist of each RTL partition throughout this early standard cell and macro placement process to accurately time the design. Being able to work at the full chip level leads to better results because all aspects of the chip are taken into account, including modules, all synthesized blocks, all placement, and even routing congestion. This makes the synthesis process repeatable and predictable. A small change to the input RTL will not result in a wildly different result. Including physical locations for all design elements leads to much more accurate congestion and timing estimations, which allow RTL designers to refine the design to better meet design requirements for area, power, and performance.
Power is a chip‐level problem, but traditional synthesis, with its limited capacity, forces power to be considered at the block level with inadequate chip-level information. RealTime Designer offers full-chip, power-aware synthesis that fully supports two major current approaches: multi‐threshold libraries and automatic clock gating. It follows the UPF power standard and supports voltage islands. During synthesis it inserts all the appropriate level shifters, isolation cells, and retention registers depending on the power policy.
You do not need a complete UPF file before performing physical synthesis because RealTime Designer can be used interactively to consider alternative power architectures. When this “what-if” analysis is complete and the final policy has been selected, RealTime Designer will write out the UPF file to be used during static timing analysis or physical design.
Capacity and RunTime
RealTime Designer brings a new approach to design creation by taking an entire chip design all the way from RTL to placed gates/macros in a single pass. Designs of tens of millions of gates can be processed with an off‐the‐shelf PC in a few hours, taking an entire chip netlist to placed gates in a fraction of the time needed by tradition synthesis tools.
The large tool capacity is matched by the fast runtime. Being able to synthesize entire chips in a matter of a few hours, as opposed to days, is more than just a straightforward increase in productivity, it lets the designer focus on the design and not the limitations of the design tool. One benefit of faster runtime is a shorter design schedule. However, even if the master schedule is driven by other considerations, then the faster runtimes with RealTime Designer can be used to find a better solution, allowing time to experiment with higher-level architectural tradeoffs.