Products A to Z - IC Design
ADiT is a fast-SPICE simulation tool that delivers the ability to obtain accurate and reliable simulation results 10X – 100X faster than traditional SPICE tools.
Calibre nmLVS™, the industry-leading physical verification tool for layout vs. schematic comparison combines accurate circuit verification with fast runtimes and interactive debugging.
Calibre Automatic Waiver provides automated recognition and removal of waived design rule violations during DRC. Calibre Automatic Waivers eliminates costly time and effort from the verification process, and ensures accurate processing of all waiver information on every DRC run.
Calibre CMPAnalyzer enhances systematic and parametric yield at smaller process nodes by simulating the changes in thickness and resistance variability, and by using automated fill capabilities to reduce resistance variability while minimizing capacitance.
The Calibre DESIGNrev layout viewer speeds full-chip design completions and tape-outs by rapidly loading, displaying and saving large GDSII and OASIS® files.
Calibre InRoute enables designers to achieve signoff-quality manufacturing closure during physical design within the Olympus-SoC place and route system.
The Calibre Interactive™ invocation GUI provides users with fast and easy access to the Calibre® tool suite, enabling designers to perform physical verification and parasitic extraction from within their familiar IC design environment.
Calibre LFD is the first production-proven EDA tool to address the urgent issue of how to manage lithographic process variability in the early stages of design creation.
Calibre nmDRC™, the industry-leading for design rule checking provides fast cycle times and innovative design rule capabilities.
Calibre Pattern Matching replaces text-based design rule checks with a visual geometry that ensures a precise and accurate implementation of the design specification.
Industry’s only programmable electrical rule checking (PERC) tool designed to address advanced verification requirements to ensure optimal design yield and improve reliability.
Calibre RealTime enables on-demand Calibre sign-off design rule checking (DRC) for custom and analog/mixed-signal design flows, improving both design speed and the quality of results by providing immediate feedback on design rule violations and recommended rule compliance.
Calibre RVE™ provides a graphical results viewing environment that can be used with all Calibre tools and popular design layout tools to reduce debug time by visually identifying design errors instantly in the user’s own design environment.
Calibre xACT 3D delivers high performance parasitic RC extraction featuring the reference-level accuracy of a deterministic field solver combined with the production turnaround performance of traditional rule-based extraction tools.
Full-chip, fast, and accurate extraction of frequency dependent loop inductance and loop resistance and automatically accounts for return path change with frequency. Fully integrated with Calibre nmLVS and xRC.
Calibre xRC™ offers a robust parasitic extraction tool that delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation.
Calibre YieldAnalyzer integrates random (critical area) and systematic (critical feature) process variability analysis using model-based algorithms that automatically plug layout measurements into yield-related equations to help you identify areas of your physical design that have higher sensitivity to variations across the manufacturing process window.
Calibre® YieldEnhancer offers an automated approach to layout enhancements that will improve yield.
The DFM Analysis Service allows designers to identify and fix litho hotspots before they commit to tape-out. It is an attractive option for startups taping out relatively few advanced node devices per year, giving them a “capital lite” way to meet TSMC’s sign-off requirements without investing in costly design data center.
When accuracy matters designers choose Eldo Classic, Mentor’s “golden” SPICE accurate circuit simulator, designed to address the complex needs of analog and mixed-signal designers.
Mentor’s new Faster-SPICE product, addresses the primary concerns of analog and mixed-signal designers, providing increased performance and capacity, especially for very large circuits, without sacrificing accuracy.
The analysis and measurement capabilities of Eldo RF help designers verify complex RF IC designs more quickly and accurately. From simple compression or intermodulation analysis to complex digital modulation, Eldo RF powerful algorithms make genuine verification a reality.
EZwave™ providing a high-capacity, high-performance graphical waveform environment for displaying and that analyzing complex analog, digital, RF, and mixed-signal simulation results.
ICanalyst is an advanced analog, RF and mixed-signal verification environment for custom IC design. ICanalyst manages the validation of custom analog ICs though process-variation, using specification-driven methodology to fully characterize design figure of merits and let you optimize design to improve yield.
Kronos Analyzer is a comprehensive library analysis and validation solution.
Kronos Characterizer Plus is a high-throughput, general purpose cell library characterization tool for standard cells, memory, IO Pad, and custom macros.
The Olympus-SoC™ physical implementation platform meets the highest demands of IC designs at advanced nodes.
Pyxis Implement, part of Mentor's Pyxis Custom IC Design Platform, provides a highly productive environment for correct-by-construction layout by rapidly loading, displaying, and saving large GDSII and OASIS® files.
Pyxis Layout, part of Mentor'sPyxis Custom IC Design Platform, provides a fast and flexible environment for layout entry and editing.
Pyxis Schematic, part of Mentor's Pyxis Custom IC Design Platform, provides a powerful and easy-to-use design entry environment with advanced capabilities that boost designer productivity.
Language-neutral, mixed-signal simulator that enables top-down design and bottom-up verification of multi-million gate analog/mixed-signal System-on-Chip designs.
Complete simulation of RF system-on-chip (SoC) designs becomes a reality when you combine the RF capabilities of Eldo RF with the mixed signal capabilities of Questa ADMS.