Complex physical designs (layouts) in 65 nm and below process nodes often use ten (10) or more layers of metallization. So, the length of supply (power/ground) nets as well as that of clock and signal nets is typically long, and the nets involve multiple layers of Vias. These Vias tend to dominate the impedance due to these nets. It is, therefore, often the case that insufficient Via placements on the junctions between Metal(N) and Metal(N+1) turns out to be the root cause of the IR drop failures, and net delays giving rise to setup and hold time violations. The other detrimental effect of Via-deficient junctions is increased heat dissipation and current crowding leading to electro-migration. Wide metals warping resulting in unreliable Via connections require redundant Via placements. Some Via-deficient junctions may barely meet redundant Via requirements, but additional Vias often make the junctions more robust. This paper discusses a simple Perl-Calibre® approach to check for and add Vias to M(N)-M(N+1) junctions that have insufficient Vias or no Vias, but could hold more Vias without violating the topological design rules checks (DRCs). The Vias are checked for and added to junctions on user-specified nets. Although, typically supply nets (VDD,VSS) are handled by the code, there are actually no restrictions on the net names as long as they are top-level net names that can be traced downwards along metal and via lines, or even other connectivity layers.