As the first step in a netlist-to-GDSII design flow, floorplanning presents the SoC designer with challenges and opportunities that affect the rest of the design flow, from block implementation, to chip assembly and top-level closure. It is particularly important in hierarchical floorplanning to quickly solve macro and IO pad placement, accurately estimate timing, power and area, create top-level power networks, and to efficiently partition the design. Floorplanning for large, complex ICs and SoCs depends on a high capacity solution that allows early timing estimations in a multi-mode, multi-corner (MCMM) context, supports all varieties of multi-Vdd flows, and offers wide flexibility between automatic and manual placements of all floorplan objects. In this paper, we review floorplanning challenges and show how the Olympus-SoC implementation system comprehensively addresses all those challenges to produce the best floorplan in the shortest time.