A spread-spectrum phase-locked loop (PLL) clock generation system is modeled and simulated using Simulink. A multi-phase voltage-controlled oscillator (VCO) along with a delta-sigma modulator is used for spreading with a triangular signal of 33 kHz frequency for an output frequency of 3 GHz. The achieved peak power reduction is 16dB at 5000ppm frequency down-spreading. The simulation time is around 4 hours for a complete period of the modulating frequency for a five order of magnitude ratio between the output signal to the modulating one. Keywords: Phase-locked loops (PLLs), spread-spectrum clock generation (SSCG), delta-sigma modulation, multi-phase VCO.