3D-IC System Verification Methodology: Solutions and Challenges
White Paper
ABSTRACT
Presents a verification methodology for 3D-ICs, including connectivity checking and parasitic extraction. Discusses new challenges and EDA tools to responds to those challenges. An example illustrates a true 3D-IC stack verification using a GDS based flow.
Related Resources
How to select specific rule checks for a Calibre...
Technology Overview 03:05How to select specific rule checks for a Calibre DRC run
This video shows you how to create specific rule check recipes for running DRC in Calibre Interactive. Rule check recipes allow you to configure and reuse specific rule checks such as metal, density, and...
How to turn DESIGNrev command-line script into a...
Technology Overview 03:32How to turn DESIGNrev command-line script into a GUI-menu based Macro
If you want to introduce your script to your co-worker to use, the best way is to make it accessible from GUI menu. So your co-worker can recognize and click the menu item to launch the script, instead...
How to find cell-references using DESIGNrev
Technology Overview 02:59How to find cell-references using DESIGNrev
This video shows how to quickly and easily find the cell references. The results can be filtered by hierarchy so you can get the results that you are interested in.