In response to the trend of ever increasing design sizes and complexity, IC designers have needed more compute power to complete design projects on time. But the growth in computing power is coming from many cores instead of increasing clock speeds, so physical design software must become highly optimized for multicore platforms. In particular, the timing analysis tasks offer the largest single opportunity for reducing design cycle time. Timing analysis is performed throughout the place and route flow. It is the fundamental “cost optimization function” for most routing decisions, and virtually every change in a layout will impact timing in complex ways. So parallelizing timing analysis and optimization can provide the biggest impact on the overall implementation flow. In this paper, we will describe how the Olympus-SoC technology achieves scalable parallelization of timing analysis and optimization throughout the place and route flow. We show example timing analysis runtimes and overall design times on multicore platforms using Olympus-SoC.
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Olympus-SoC, parallel computing, place and route, Place_and_Route, placement, timing analysis, Timing Constraints