An Innovative Approach to High Frequency Analysis of IC Layouts
IP Scoring Using TSMC DFM Kits
This talk proposes a method of scoring IP from cell to block level for DFM quality which provides a basis for building high DFM quality into your SoC and gaining maximum yield potential.
Layout Pattern Dependence-Aware Highly Accurate Simulation Flow with Calibre nmLVS
In today’s nanometer processes, the “layout pattern dependence” that causes variations in the electrical characteristics due to the shape around MOSFETs is becoming more significant. In response to this,...