Automated Yield Enhancements Implementation on full 28nm Chip: Challenges and Statistics
High Performance Electrical Driven Hotspot Detection Solution for Full Chip Design using a Novel Device Parameter Matching Technique
With the continuous development of today’s technology, IC design becomes a more complex process. The designer now not only takes care of the normal design and layout parameters as usual, but also...
Smart Double-Cut Via Insertion Flow With Dynamic Design-Rules Compliance For Fast New Technology Adoption
As IC technologies shrink and via defects remain the same size, the probability of via defects increases. Redundant via insertion is an effective method to reduce yield loss related to via failures, but...