This paper discusses the features implemented in a Design for Manufacturability (DFM) checker for Critical Feature Analysis of Very Deep Sub-Micron (VDSM) layout designs. This checker leverages Calibre® Yield Analyzer (YA) and Yield Enhancer (YE) functionality, as well as Calibre TCL Verification Format. A central feature of the deck is the identification of opportunities where a layout situation can be improved in a simple, straightforward manner without increasing area inside the top cell boundary. The purpose of such optimization is to increase design robustness to systematic and random yield loss mechanisms and reliability issues without increasing silicon area and cost. An overview of the improvability algorithms implemented using YE features is described, with focus on specific examples of macro code and improvability results on real-life layout cases. Also presented is the use of YA functionality to quantify the gain possible from the application of identified improvements in terms of DFM score. The benefit of this feedback is that it helps designers in prioritizing and selecting the layout improvements to make. Application of the proposed layout optimization flow is finally demonstrated on a 90nm SRAM memory cut design for automotive applications.