Deflecting the Design Diversity Dilemma: Methods for Improving Mixed-Signal Post-Layout Analysis in an SoC Flow

ABSTRACT

Analog/mixed-signal (AMS) SoC designs are seeing a sharp increase in analog and RF content, spurred by the demand in the consumer electronics industry for more complex feature sets in products such as wireless equipment. AMS designs depend on high-performance integrated circuitry to achieve robust functionality, such as memory subsystems, adaptive filters, RF modules, phase-locked loops and high-speed interfaces for communication between chips and systems. As more functions are combined on a single SoC, AMS SoC designers face the challenge to verify these diverse design styles and functionality in their entirety while meeting aggressive time-to-market demands and fulfilling high manufacturing yield expectations. Statistics show that nearly half of all mixed-signal designs fail first silicon. Deep submicron effects can influence circuit timing, power consumption and reliability at nanometer process nodes, adding an additional verification burden for the SoC designer.

At final chip assembly, a mixed-signal post-layout analysis solution needs to ensure design integrity through high-performance mixed-level simulation of the full chip, including parasitics. Traditional SoC design and verification approaches have to be reevaluated to successfully integrate state-of-the-art mixed-signal technology to achieve accurate and streamlined full-chip SoC design closure.