High Performance Electrical Driven Hotspot Detection Solution for Full Chip Design using a Novel Device Parameter Matching Technique
Automated Yield Enhancements Implementation on full 28nm Chip: Challenges and Statistics
This paper shares the details of the Yield Enhancements that were done at 28nm full chip level sharing the complexity involved in implementing such a flow and then the verification challenges involved ,...
Smart Double-Cut Via Insertion Flow With Dynamic Design-Rules Compliance For Fast New Technology Adoption
As IC technologies shrink and via defects remain the same size, the probability of via defects increases. Redundant via insertion is an effective method to reduce yield loss related to via failures, but...