Macro Placement in Olympus-SoC
Why IC Designers Need New Double Patterning Debug Capabilities at 20nm
Jean-Marie Brunet, Director of DFM Product Marketing, discusses Mentor's history of collaboration with TSMC and highlights their work on design enabling support for 20nm.
Double Patterning from Design Enablement to Verification
Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal layers. We discuss the unique design and process characteristics of LELE DP, the challenges...
Self-aligned double-patterning (SADP) friendly detailed routing
Among the possible double patterning strategies, self-aligned double patterning (SADP) has moved from Flash-only processes to more general purpose devices. The reason is that while lithoetch-litho-etc (LELE)...