Parasitic Effects, Nanometer Silicon Modeling and Calibre xRC

ABSTRACT

As process technology heads below the 130nm node, the shrinking geometries of nanometer designs have revealed significant concerns over signal integrity and timing closure. With 90 nm designs in production, 65nm in view, and copper technology commonplace, serious challenges are confronting designers that have profound impact upon the success of today's sophisticated analog mixed-signal (AMS) designs. These challenges stem from a combination of factors that emerge in nanometer scale design, such as shrinking feature sizes, finer line widths, longer interconnect, more routing layers, and more analog content.