Pravin Madhani at DAC 2012

Why IC Designers Need New Double Patterning Debug Capabilities at 20nm

Jean-Marie Brunet, Director of DFM Product Marketing, discusses Mentor's history of collaboration with TSMC and highlights their work on design enabling support for 20nm.

TAGS: 20nm, double patterning

Macro Placement in Olympus-SoC

This video shows the automatic macro placment capabilities in the Olympus-SoC place and route system. It also shows examples of the improved design metrics the Olympus-SoC macro placer achieves.

Double Patterning from Design Enablement to Verification

Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal layers. We discuss the unique design and process characteristics of LELE DP, the challenges...