Reducing Physical Verification Cycle Time

ABSTRACT

Sign-off for IC tape-out has undergone dramatic changes over the past several years. The size and complexity of nanometer IC design and the volume of geometric content for related layouts all skyrocketed. Additionally, extensive changes occurred in the processing requirements for nanometer design processes. Physical impacts that we once could ignore now have measurable electrical effects.

As a result, ensuring that the original design intent is maintained is increasingly difficult. Identifying these new defect mechanisms puts a new burden on physical verification runtimes. Worse still, due to the complexity of these effects, debugging a problem through layout modifications without generating some new problem is more challenging, requiring more verification iterations than ever before. Given these impacts, the time required to iterate from design to a physically- and electrically-clean layout in these designs can rapidly overrun production schedules and delivery dates.

Clearly, new verification strategies are needed. All aspects of the physical verification cycle, from physical verification run times to the time required to identify, understand and debug design violations, must be re-evaluated. Engineers must be able to identify new complex physical interactions and characterize all physical, topological and electrical failure mechanisms associated with new process. Maintaining real-world production schedules, however, means increasing the number of iterations required to validate fixes while decreasing the total runtimes for each component. Design violations must be presented as clearly and efficiently as possible, to reduce debugging time, and approaches that reduce the time required to re-verify the impact of changes to a design must be implemented.

Calibre provides the most comprehensive and forward-looking functionality for performing DRC, LVS and DFM simulations. Through hyperscaling technology and the ability to utilize specialized cell processor architecture, Calibre ensures the fastest possible runtimes. The advanced debugging features of Calibre RVE presents all failure mechanisms to the user in a simple interface, directly within the engineer's design environment. With incremental verification and debug, Calibre lets engineers validate the impacts of design modifications without waiting for DRC runs to complete. Together, these capabilities offer the ability to dramatically reduce the total physical verification cycle time.