The growth in the system-on-chip (SoC) market is fueled by the need to increase performance and reliability while reducing overall system costs. This is exemplified by the recent introduction of Xilinx’s newest FPGAs, the Virtex-4 family.
ASIC-style integration and performance is now available in programmable logic. This means that FPGA designers need access to newer electronic design automation (EDA) tools and methodologies to maintain design efficiency and productivity. Hardware/software (HW/SW) co-verification is an example of one ASIC methodology that has recently gained relevance for platform FPGAs. In this article, I will introduce the concept of co-verification, and will describe its role, relevance, and realizable benefits in the context of programmable systems. I will also explain the actual development work done in cooperation with Mentor Graphics to extend existing IBM PPC405 HW/SW co-verification solution to more effectively target Xilinx devices.