Via Doubling to Improve Yield
White Paper
ABSTRACT
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Related Resources
Foundry Solutions Video Blog: TSMC OIP Conference
Technology Overview 05:40Foundry Solutions Video Blog: TSMC OIP Conference
At TSMC's Open Innovation Platform (OIP) Ecosystem Forum, Mentor made technical presentations on four different topics, two of them co-presented with TSMC and LSI Corporation. Those presentations are described...
TAGS: 20nm, Foundry Solutions, TSMC
Aerial Image Retargeting (AIR): Achieving Litho-Friendly...
White PaperAerial Image Retargeting (AIR): Achieving Litho-Friendly Designs
In this work, we present a new technique to detect non-Litho-Friendly design areas based on their Aerial Image signature. The aerial image is calculated for the litho target (pre-OPC). This is followed...
Fast Process-Hotspot Detection Using Compressed...
White PaperFast Process-Hotspot Detection Using Compressed Patterns
This paper presents an approach for compressing litho hotspot pattern library that complies with general purpose pattern matching engine. This approach incorporates two techniques to achieve optimal pattern...