Why IC Designers Need New Double Patterning Debug Capabilities at 20nm
Macro Placement in Olympus-SoC
This video shows the automatic macro placment capabilities in the Olympus-SoC place and route system. It also shows examples of the improved design metrics the Olympus-SoC macro placer achieves.
Double Patterning from Design Enablement to Verification
Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal layers. We discuss the unique design and process characteristics of LELE DP, the challenges...
Self-aligned double-patterning (SADP) friendly detailed routing
Among the possible double patterning strategies, self-aligned double patterning (SADP) has moved from Flash-only processes to more general purpose devices. The reason is that while lithoetch-litho-etc (LELE)...