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IC Design Customer Success

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Calibre Products

“The thing that pushed us to Calibre was the speed. Some of the engineers here had developed a new quick design flow in a compact process. We were struggling with Assura (running 20+ hours). Without major tweaking, Calibre was able to run in less then 5 hours.”

Jake Wright, AMI Semiconductor | source: DeepChip

“Calibre's extensive rule file coverage, design-style independence and on-time customer support made it the best choice for the complex designs our customers are creating. Selecting Calibre ensures customers a confident design transfer and a smooth manufacturing process”

Stephen Kuo, Design Service Department Manager, Technology Development Unit

“One thing I like about Calibre DRC is that I have ability to verify and record all Design Rule Waivers. I can reload this waived file during iteration of refining and tweaking design at last stage, the waived errors are all marked already. It saves huge time when I have over a thousand markers in a design deviating from the foundry Design Rule”

Michelle Lee, Guidant Corp. | source: DeepChip

“The Calibre tool is production-proven and offers a single, robust platform from design to silicon. The fact that the Calibre tool is an industry standard worldwide was also a major factor in its selection as our internal standard”

Yao Zeqiang, Ph.D., Deputy Director, Product Engineering Department, Hau Hong NEC

“Calibres robust extraction syntax and circuit compare capabilities allow it to properly check even the most difficult analog circuitry without impacting full-chip performance.”

Carl Dickey, Mixed-Signal Strategist, IBM Microelectronics SiGe BiCMOS Foundry

“Our long history and successful track record with Calibre/xCalibre were key factors in our selection process. Calibre and xCalibres excellent mixed-signal/RF capabilities, including advanced device recognition, extraction accuracy, and tight design environment integration, will provide us with the tools we need to offer a best-in-class production-proven environment for our customers advanced semiconductor designs.”

Marco Racanelli, Executive Director of Research and Development, Jazz Semiconductor

“Calibres robust extraction syntax and circuit compare capabilities allow it to properly check even the most difficult analog circuitry without impacting full-chip performance.”

Rodney Jacks, Senior CAD Engineer, Motorola

“Calibre offers a unique combination of performance, accuracy, and capability allowing us to implement an optimal recipe for our 0.095 micron process. Calibre is already in use with our 0.180 and 0.150 micron technologies, and NEC is aggressively moving forward with advanced semiconductor processes. Calibre is a key enabler in accelerating this schedule.”

Dr. Kazuhiko Takamizawa, Senior Manager of System LSI Design Engineering Division, LSI

“Without Calibre, we were unable to properly verify designs with more than a million gates. Calibre offers speed, capacity and ease of use with our advanced technologies. It also allows us to compete more effectively with other leading manufacturers in this market segment.”

Jamshed Qamar, Vice president, ASIC Business Development, Oki Semiconductor

“Selecting Calibre as the standard for our verification tool platform ensures that our customers designs are flawless and the ensuing manufacturing process is smooth. Calibres extensive rule file coverage and advanced resolution enhancement technologies make it the best technology choice for our customers and partners.”

Victor Kwong. Vice President of Design Solutions, Silterra

“Calibres extensive rule file coverage is production-proven, ensuring that our customers and design partners gain a smooth transition to manufacture. Advanced device recognition capabilities and design-style independence make Calibre one of the best choices for the complex designs our customers are developing.”

Dr. James Sung, Vice President of Marketing and Sales, SMIC

“We now use the same comprehensive Calibre rule files for cell/block verification as we do for full-chip verification. This gives us the confidence that the design will be successful through tapeout with the least amount of iteration necessary. After many successful silicon runs at .12 micron using Calibre OPC tools, we have standardized on it for our high-volume, production-level .10 micron processes.”

D. Goubier, Reticle Assembly Team Manager, Central R&D, STMicroelectronics

“Calibre LVS and DRC is still the industry leader for cell level to full-chip backend verification. Calibre xRC is essential for the design process as it can provide parasitic data in various formats that can used by simulation tools (ie., spice, DSPF, SPEF). The availability to run on 64-bit linux multi-processor machines allows for reasonable full-chip debug.”

Steven Chin, Stretch, Inc. | source: DeepChip

“Calibre is unfettered by any restrictive proprietary format or framework, which made it a perfect fit in our overall CAD strategy. And its multi-threading capability really made this tool fly on 12 CPU machines in our compute farm.”

Ward Verycrusse, Senior CAD Architect, Sun Microsystems

“Combining Mentor Graphics Calibre rules to TIs design tool capabilities will give our customers the ability to perform comprehensive physical verification of ASIC and mixed-signal system-on-a-chip (SoC) designs. We are excited to use Calibre to help enable widespread use of TIs silicon technology with our leading customers.”

Bill Giolma, Worldwide Customer-Owned Tooling Manager, Texas Instruments

“We chose Calibre because it offers a single design-to-silicon platform that meets our requirements for performance, capacity and accuracy. Using Calibre not only streamlines our internal processes, thereby improving time to market, but also ensures that our customers receive fully qualified and extensive rule file support, which gives them a distinct market advantage.”

Sergio Kusevitzky, Vice President of IP and Design Services, Tower Semiconductor

“Design engineers can rely on high-quality Calibre rule files to verify their designs for TSMC silicon. Not only do we put them through TSMCs rigorous double-blind QA procedure, but, because Calibre has been used to verify designs in our production environment for the last 2.5 years, we know that they cover real-world design conditions.”

Genda Hu, Vice President of Marketing, TSMC

“At the 90nm technology generation, it becomes increasingly important for our customers to seamlessly move from design to successful silicon due to the complexity of modern SOC designs. Calibre rule files, production-proven for five years at UMC, receive extensive qualification to smooth the transition from tape-out to manufacture, thus reducing cost and time-to-profit for our customers.”

Ken Liou, Division Director, Design Support Division, UMC

“After using all three of the major hierarchial tools, you'd have to work really hard to make me give up Calibre. The biggest reason is that its debugging capability is so far ahead of all the other tools out there.”

Ron Talaga, Vitesse Semiconductor | source: DeepChip

“X-FAB will offer its customers complete Mentor EDA support for the newly developed X-FAB master kits. These mixed-signal design kits support the complete Mentor verification product line with Calibre DRC and Calibre LVS for physical verification and xCalibre for parasitic extraction, as well as the newest simulation tools based on the Mentor Graphics IC Flow and Design Architect-IC, including ADVance MS, Eldo and Modelsim.”

Thomas Ramsch, Manager Design Support, X-FAB Group


“We worked with Mentor Graphics to qualify Olympus-SoC for our 40nm process. All our requirements were met and we expect designers to benefit as they move to TSMC's most advanced production process.”

Sameer Halepete, vice president of ASIC Engineering at NVIDIA

“We worked with Mentor Graphics to qualify Olympus-SoC for our 40nm process. All our requirements were met and we expect designers to benefit as they we expect designers to benefit as they move to TSMC's most advanced production process.”

S.T. Juang, Senior Director of Design Infrastructure Marketing, TSMC

“We used Olympus-SoC to tape out an advanced set-top box chip containing 12 million gates and manufactured using an 80nm process. We are extremely pleased with the Olympus-SoC product's ability to deliver this first-pass functional silicon, and we are impressed with the overall quality of results including design rule check (DRC) clean routing, multi-corner-multi-mode timing closure, and fast runtimes for large capacity chips.”

Thierry Bauchon, R&D Director, Home Entertainment & Displays Group, STMicroelectronics

“We used the new timing and optimization technology in Olympus-SoC for the extremely complicated EMMA design, which has over 30 million gates, four modes and four corners, a 200MHz main clock, and over 150 derived clocks. We are very impressed with Olympus-SoC’s performance improvements, which provided almost a factor of four reduction in our design closure time.”

Mr. Masao Hirasawa, General Manager, Digital Consumer LSI Division, NEC Electronics Corporation

Analog/Mixed-Signal Verification Products

“Our investment in a new methodology encompassing full mixed-signal and RF verification using the Mentor simulation suite paid off immediately. For the first time we were able to completely verify this next-generation wireless chip prior to manufacturing.”

Morten Kroman, Vice President Research and Development, Widex

“STMicroelectronics is a leader in delivering a complete CMOS 32nm design solution to our customers that optimizes design productivity for low power designs without compromising the performance, quality or the silicon correlation. To achieve this goal, we have built a reliable ecosystem with our long term partner, Mentor. We worked together to develop a robust solution for the design and characterization of our libraries for our worldwide design teams.”

Gérard Mas, CMOS Libraries Group, Director of the Technology Research and Development, STMicroelectronics

“We are impressed with the performance we observed from ADiT software in several mixed-signal projects, as using ADiT helped us meet our time-to-market criteria, ADiT is now one of our standard sign-off tools for mixed-signal IP that targets our 0.13-micron and below processes.”

Ken Liou, Director of Design Support Division, UMC

“Given the data volume, manual inspection is not an option. The entire characterization must be a 'push-button' automated process, even when each individual simulation is a challenge with these advanced technology nodes and associated models. We developed quite a sophisticated infrastructure to achieve this goal, and Mentor demonstrated the required reactivity, resources, and engineering commitment to let us reach the desired productivity level.”

Laurent Bergher, CMOS Standard Cell Libraries Group Manager, STMicroelectronics

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