STMicroelectronics Achieves Performance Improvements Using Questa ADMS
STMicroelectronics Display Driver Team in Catania Achieves Outstanding Performance Improvements Using Questa ADMS for their Mixed-Signal Simulation Methodology
For system-on-chip designers, mixed-signal simulation is becoming increasingly challenging, especially as a competitive market is pushing the need for first-time silicon success in a shorter design time, not only for digital design, but also for analog and mixed-signal designs.
“The results have been outstanding in terms of performance improvement, flow efficiency, and number of bugs spotted.”
Just a few years ago, only two kinds of simulation were available for mixed-signal designers: digital simulation of VHDL or Verilog code and analog simulation of a SPICE netlist. A mixed-signal circuit could be simulated at either the transistor level after code synthesis or with a digital behavioral model for the analog blocks.
These options didn’t provide for simulating the analog-digital interaction, took long run times, and were inaccurate because modeling complex blocks such as charge pumps, oscillators, and digital-analog circuits is not a simple, straightforward process.
A team of engineers designing VGA display drivers at STMicro- electronics in Catania, Italy, implemented an alternative method that allowed them to simulate both analog and digital in their mixed-signal design and to verify that the design functioned as intended. Their circuit consisted mainly of analog blocks with 1 million transistors, large RAM, and four charge pumps.
Because of the specific architecture of the chip and the frequent bugs they encountered, they wanted to be able to verify system functionality and interaction between analog and digital blocks, as well as simulate the effects of the load in a real application.
They also wanted to identify mismatches with specifications or where a misunderstanding of the design was leading to problems, to verify the register default values in the digital core to reduce bugs in the VHDL, and to spot possible forward-biased diodes and cross-conduction caused by floating gates or low voltage.
Often dealing with these issues requires a complex methodology using different tools to verify different aspects of the design. The team already had proven methods for coverage-driven and electrical verification but they needed to define a top-level functional verification method based on the mixed-signal simulation.
Coming up with such a solution was a collaboration between the STMicroelectronics verification team, consisting of mixed signal and electrical verification engineers, a Mentor Graphics modeling engineer in Cairo, Egypt, and a Mentor applications engineer who set up the verification environment.
STMicroelectronics team (starting from left): Antonio Maimone, Bruno Cavallaro, Rosario Plumari, Angela Gambina, Rosario Miritello, and Riccardo Condorelli.
The verification team used Eldo® for electrical verification of the analog blocks. They also used Fast SPICE to speed up simulation because a SPICE simulator can’t simulate 1 million devices simultaneously at the transistor level. They found, however, that they lost accuracy with this method.
“Fast SPICE was ten times faster than Eldo but it was not accurate enough. With Eldo in fast mode, we took more than 100 hours to simulate only the charge pumps,” says Antonio Maimone of ST- Microelectronics. And with Fast SPICE it took longer to set up the simulation environment and variables. This bottleneck drove the need for a new methodology.
The STM team’s past approach had been to work from the design layout; this time, they wanted to use a method that divided up the analog and digital paths based on functionality. They decided to use Eldo for electrical verification and Mentor’s ModelSim®, which they had been using for digital blocks.
A novel aspect to their alternative method is that they applied VHDL-AMS behavioral modeling to analog blocks and created models that allowed them to visualize the circuit’s analog behavior.
“Our challenge was to understand the top level when we do the simulation — it’s not easy. You don’t just build the model, put it into simulation and it works immediately. The Mentor modeling engineer worked with us to understand the model and fix it to fit into the block level. This was a chalTwolenge for us because we hadn’t used a model before,” says Maimone.
Two possible solutions for mixed-signal chip-level simulation.
The Mentor modeling engineer wrote the model for them so that it could be used to establish a methodology that everyone could follow.
When the team tried to use Eldo to run the entire simulation, it Waveform comparison of actual circuit and simulation models.would take hours, but with the new method it took seconds (see table). By modifying the tools and using their alternative simulation method, they were able to see the behavior (waveform) of the chip so they could verify its functionality, something they had been unable to do before. They were also able to run several integrations, a common practice with digital, but not done in analog.
The new method was a success: the team was able to see the behavior, verify whether the function was good or not, and to pinpoint more bugs before tapeout.
Waveform comparison of actual circuit and simulation models.