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Aeroflex: Questa ADMS and OVM

The Questa® ADMS mixed-signal simulator and the Open Verification Methodology (OVM) deliver easy access to advanced verification technologies, greater control, and fast simulation speeds, boosting productivity and helping Aeroflex Colorado Springs get their silicon to work right the first time within a tight schedule. Combining ADMS and the OVM, Aeroflex bridged the gap between the digital and analog verification domains to find and fix critical problems.

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The ease of use of Questa ADMS made it possible for us to to complete our phase of the project on schedule.”


Aeroflex’s Microelectronic Solutions division in Colorado Springs provides HiRel (high reliability) standard and custom integrated circuits and circuit card assembly for the aerospace, highaltitude avionics, medical, and other critical-use markets. The increasing complexity of their designs was straining the conventional ad hoc approach to analog mixed-signal (AMS) verification. Modern mixed-signal designs include multiple feedback loops between digital and analog components, making integrated mixed-signal simulation essential for early detection of elusive problems that can develop at the analog/digital interface.

The Aeroflex analog team was able to adopt a structured, AMS verification approach by adopting Questa® ADMS and the OVM to increase productivity, reduce errors, manage the verification process, and establish a reusable verification infrastructure that will reduce future duplication of effort. 

Modern Designs, Modern Solutions

The Aeroflex team qualified this methodology during the development of a 16-bit, 80-MSps, CMOS pipeline analog-to-digital converter (ADC), which was designed in a monolithic CMOS process using Aeroflex’s technology for harsh operational environments. The target noise (77dBFS SNR) and distortion performance (100dBc SFDR) make this ADC ideal for those telecommunication and imaging data processing applications posing the most severe electrical and environmental requirements. Digital control constitutes about 30 percent of the design, while 70 percent of the circuit is analog.

Aeroflex plans to use designs with similar functionality and control logic in the future as their products evolve. This justified their investment in a reusable verification infrastructure, such as the OVM. At the same time, they did not want to impose the requirement that analog engineers become instant OVM experts. The implementation plan took both considerations into account. Additionally, the complexity of their design’s AMS activity required that they exercise great economy and make intelligent choices to complete their verification on time. For these reasons, they wanted to use the OVM with an AMS tool to efficiently attain their defined goal of verifying the interactions between the digital and analog domains—something traditional SPICE tools are not equipped to do.

Traditional analog tools also cannot handle the hundreds of combinations of bits and sequences that need to be handled by the design. Without a tool that is able to co-simulate the interactions between digital and analog, many potential mistakes are bound to be missed when running separate analog and digital simulations.

After considering the leading mixed-signal solutions, Aeroflex determined that Mentor Graphics had the required solution in both its Questa ADMS mixed-signal simulator and OVM expertise. Questa ADMS proved superior in terms of ease of use, simulation speed, and reuse. As originators of the OVM, Mentor was also able to provide expert support to help Senthil Vinayagam, Principal ASIC Design Engineer, develop a template and interface that made OVM adoption virtually transparent for the analog team. As a result, analog designers—who were understandably wary of using a complex methodology based on an unfamiliar language—experienced how easy it was to use. They came to fully embrace it for the bugs it uncovers, the quality assurance it provides, and the productivity it delivers.

Even though ease-of-use was one of the benefits of using Questa ADMS and the OVM, both were new to the analog members of the team; and like any richly featured solution, the promised benefits require some upfront effort. A major selling point for Mentor was that it had the expertise to flatten the learning curve and provide essential support once the environment was up and running.

“This is new ground, and it’s a good way to solve the problems of the mixed mode simulation,” Mr. Vinayagam observes. “It’s a great tool: with ease-of-use and the methodology. The Mentor team was very helpful in setting this up and participating. They didn’t just come here and look at things from their tool’s perspective; they looked into the SPICE and into the design, and the Mentor AE understood our technologies well enough to make the tool work with our designs. That kind of expertise is very important.”

ADMS Speed and Precision

As one of the Aeroflex analog designers on the team, Alfio Zanchi, Ph.D., Senior Principal Design and Applications Engineer, was already familiar with Mentor’s Eldo SPICE simulator, but he had never used a true mixed-signal simulator that incorporates digital Verilog modules and transistor-level netlists before.

Fortunately, because Questa ADMS features are a superset of those in Eldo, Dr. Zanchi was productive immediately in the mixed-signal environment. This was partly due to the tight integration and transparency between the Eldo and Questa simulators. The Eldo analog engine and Questa digital engine are integrated, as are the parts of the design described as Spice netlists and Verilog modules. The tools even use the same ASCII files to aid the initial convergence and the same waveform viewer.

“Questa ADMS capitalizes on the speed of Eldo, which is an excellent engine,” Dr. Zanchi says. “The other solutions were not as fast or as comprehensive as the combination of ADMS and Eldo. Speed and precision are definitely something that matters for our designs. We were in crunch time, and we would have never made it without the seamless integration of Eldo and Questa ADMS.”

Speed and precision were especially important to avoid any malfunctions (such as long limit cycles, potentially in the hundreds of microseconds) that may have occurred in the Aeroflex design. Importantly, the tool must be able to maintain sufficient precision at higher speeds. Otherwise, even after a few days of simulation, the run will not cover more than 100 microseconds and will miss any limit cycles that might occur beyond that time interval. “Questa ADMS allowed us to see many more points than 100 microseconds,” Dr. Zanchi reports, “even if we ran a simulation for only one day.”

Another important benefit was the ability to reuse Eldo convergence files in Questa ADMS. “Convergence presents one of the more serious problems for analog design simulation,” Mr. Vinayagam observes. “We were able to use Eldo’s convergence files in the ADMS environment so that the Spice convergence happened very easily. That’s not only an ease-of-use benefit but also a reuse benefit.”

Questa ADMS was used to focus on the interaction between the digital and analog parts of the design, after the analog and digital portions had been independently verified at the block level. “Defining the scope makes our use of the Questa ADMS tool more efficient by focusing on the interaction between the digital and analog domains,” explains Mr. Vinayagam. “Though this may sound very limited, Alfio and I found many problems, which we were able to fix.”

“Using ADMS we were able to verify all of the complex control sequences and combinations of bits in our design,” Mr. Vinayagam continues. “That makes the simulation more realistic and it is easier for the analog designers to check, for example, that when they put in a sequence the analog blocks behave as expected. In some cases the analog blocks did not respond to the digital stimulus as expected; we were able to look at those and come up with fixes—this was very critical because if we hadn’t caught these it could have caused serious problems when the silicon came back.”

With Questa ADMS, it is extremely easy to observe digital and analog signals on the same waveform viewer. An important example was improved visibility of Power-On Reset (POR) circuit activity and the analog signals that control this behavior. “You can put down a vertical cursor and see the POR has been reset as a response to something that has occurred in analog,” Dr. Zanchi explains, “and you can see analog-cause and digital-effect exactly aligned on the waveform panel of the block simulation. That was very easy to do.”

Compared to its predecessors, this new member of the Aeroflex ADC family has a larger number of programmable parameters for tuning the part to suit the customer’s needs. That led to a growth of the part’s digital content, which in turn spurred the need for more complex parallel and serial interfaces. “Simulation with ADMS was paramount because we had to verify the compatibility of the parallel programming of the ADC through external pins, and the serial programming of it through the 3-wire SPI.” Dr. Zanchi explains. “We had to verify that they could produce the same effect without conflicting with each other.”

Another challenge was to check that late optimizations made to the analog circuits did not break the communication with digital commands. “The last thing you want is to go in the lab, try to optimize the linearity of the circuit, and only then realize that whatever was put in place does not work—because you cannot control the internal analog circuit through the digital interface,” Dr. Zanchi relates. “All these aspects can be simulated through ADMS, and that’s what we need.”

Reuse and Control with OVM

The importance of OVM to Aeroflex can be summarized as control and reuse. A conventional OVM arrangement of agent, monitor, and driver was constructed for the digital control interface of the device. A test definition language of SystemVerilog task calls reflecting the analog designer’s view of this class of ADC was built on top of the standard test definition components of OVM. The analog engineers, who had never used SystemVerilog, could readily modify the test without needing to know the intricacies of OVM or having to resort to analog low-level pin wiggling of the control interface—all the while benefiting from the assurance that the proven control interactions would always be handled correctly.

“Senthil came up with a SystemVerilog task call so that I could write anything I needed in a natural way, and control the testbench without having to understand what’s going on behind the scenes,” Dr. Zanchi explains. “The syntax is straightforward, and I can see the exact point in the file where I can instance, for example, a command to change the internal status of a bit. For someone who has never used ADMS or any other mixed-signal simulator, to receive a template from a digital expert and be able to modify it effectively was a big advantage; for me, and for the other analog designers as well.”

This is what Mentor calls a firmware view of the chip: using a SystemVerilog interface, the OVM provides an intuitive way to control the chip. The digital engineer describes how the chip works and provides this to the analog designer as a template. For example, the internal functions are identified with the same names used in analog. The analog designer simply fills out the form, using terms he or she is familiar with to run the desired sequences and function calls. This enables analog designers to use powerful OVM features without having to learn a new language and without having to become OVM experts.

The ability to reuse parts of test infrastructures is a primary motivation for using OVM. This is a good match for analog design because complex analog drivers and monitors can be written once and then easily reconfigured for new designs, leaving more time for testing more functionality of the circuit.

“There are two types of reuse with OVM,” says Mr. Vinayagam. “One is reusing a testbench that was created for some other chip. If the product is similar, we can bring in the similar environment for the same thing quickly. The other type of reuse is on the same product; taking the OVM environment testbench used for digital verification and incorporating that into the ADMS testbench. I can easily migrate my digital testbench into the ADMS testbench within three days, five at max, and start running the ADMS simulation. Anybody that’s doing mixed-signal design can benefit from reuse, so this is a very useful flow.”

Critical Problems Found

One of the critical errors found using Questa ADMS had to do with the fact that the new ADC design can be used with either a dual or single supply. The different power-up sequence of the two cases makes it critical to ensure that the POR circuit is functioning correctly during power-up transient events. Using Questa ADMS, the team discovered that a limit cycle was occurring. Basically, even though the supply was correctly turning on, internally the POR analog circuit entered a limit cycle and the part periodically reset itself. Finding one problem like this can justify the entire investment in mixed-signal verification.

“The limit cycle could have killed all the chip functionality had it entered that mode,” says Dr. Zanchi. “If you can’t simulate the interaction between the digital and the analog, you won’t be able to find this. Because we were able to observe this in simulation, we were able to identify the cause of the cycle and work on the delay, which is intrinsic between the analog POR detection circuit and the related digital signals. By modifying some timing filters on the analog side to shorten that delay, we were able to avoid the onset of the limit cycle. Without ADMS we would have missed this.”

Another major problem found using Questa ADMS involved the transparent dither internal function. The specification, as passed from the chief architect to the digital and analog designers, had an incorrect dither bit weight. Simulating with Questa ADMS made it possible to detect this error.

“The dither function was having some digital values coming out of the digital core,” Mr. Vinayagam explains. “It was a dynamic interaction between the analog and the digital, and the dither value was more than what it was supposed to be. Fortunately, this was exposed by the ADMS simulation, and we fixed it.”

“The correct functionality of the dither mode ensured through ADMS enabled us to virtually eliminate distortion tones with small input signals,” Dr. Zanchi reports. “This is the perfect complement to large-signal performance for an ADC targeting 100dBc SFDR.”

A New and Trusted Tool

Ease-of-use, simulation speed, an interactive waveform interface, the seamless integration of digital and analog, and indispensible support not only led to a higher quality design and a successful tape-out but also earned OVM and Questa ADMS a key role in new and future projects. Even when they haven’t found problems in a design, the designers are happy the tool gives them the reassurance that everything is fine.

“We have been using ADMS extensively,” Mr. Vinayagam reports. “For every digital design I participated in since the Mentor AE set it up, I have been able to steer the analog designers to Questa ADMS. The analog designers are very happy with the addition, especially when they find problems they might have otherwise missed.”
As one designer told Mr. Vinayagam, “It’s a very good tool. We have saved a whole bunch of money by using this.”

Speed and precision are definitely something that matters for our designs. We were in crunch time, and we would have never made it without the seamless integration of Eldo and Questa ADMS.”


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