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New Router Saves Time and Improves Custom Design Performance

Routing for custom and analog/ mixed-signal designs (AMS) is different than routing for standard cell-based digital ASICs. Place and route (P&R) tools for digital-only ICs operate in a flat abstracted environment, whereas custom and AMS routing needs to be done in a hierarchical environment.

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 Almost all analog signals use non-default constraints while digital signals use nominal rules. Approximately 85% of digital signals fall into default specifications for the process technology, but it’s the opposite for custom and AMS signals where 85% of those signals are unique, with a complex set of constraints. Also custom and AMS designs don’t use a regular power mesh. Each cell’s power is unique, and cells can have multiple power domains. Historically, it took a tremendous manual effort to route pre-wires and to implement specialized routing for matching, symmetry, and shielding. These signals require special attention; and, as a result, custom and AMS designers need the ability to precisely control the routing.

 At a leading semiconductor company, a design team was using the company’s SOC routing group to accomplish top level routing for a custom IP block they were providing into an SOC. In the company’s SDL design flow, the designers did high-level resource planning for block placement, and connectivity, and they used manual bottom-up implementation for the lower levels of hierarchy. The top levels of hierarchy were placed by hand and routed by exporting blocks to the standard cell P&R team. Results were then imported back to the layout editor.


In this traditional flow, the design team had to make a special effort to keep the P&R tool from clobbering or loading down sensitive parts of the custom layout by creating complex abstracts for their IP. These abstracts would get out of sync with the actual layout, which caused DRC or electrical problems found upon data merge that had to be fixed. The efforts to model each cell limited the team to only using automated routing at the top two levels of hierarchy, forcing them to manually route all other levels. In this traditional flow, the design team was able to get only one iteration for their IP before tapeout because of the time it took to manually route all of the lower level cells. Because they were dependent on another group to do routing, they had to wait in line for the P&R group to do the layout. Furthermore, the tools had a lack of good ECO capability, which made for long iterations when changes were needed in the custom logic and they were put back into the P&R queue.

The lead engineer felt they were wasting the P&R team’s time running small blocks, plus the P&R team wasn’t familiar with the circuit which made it difficult for them to choose tradeoffs during the routing. The lack of good interoperability between P&R and custom layout tools also meant they spent a lot of time importing and exporting data and ensuring that data was preserved. It was just taking too long to iterate the layout.


The new Pyxis custom router was demonstrated to the design team, routing a section of their IP. What would have normally taken a week to route was finished in a few minutes and saved one-third of the space in the layout. With the new custom router, they realized that, for the first time ever, they had the potential to be able to iterate more, ensuring their ability to deliver a better design while saving time.

With the Pyxis custom router’s fast interactive environment, they were able to quickly set constraints, route some or all signals, extract and report net parasitics, delete routes, and re-constrain and route again. Each iteration happened in seconds or, in the worst case, minutes, and the tool was easy to learn and use.

The lead engineer determined that they could save cycle time and improve the quality of design by bringing the router into the custom layout editing environment. He targeted time and schedule sinks such as:

  • removing the need to build abstracts for hierarchical cells,
  • reducing manual routing by using the router at all levels of hierarchy,
  • using the router to reduce LVS and DRC errors and, therefore, the time to find and fix,
  • removing the need to involve a second group.

He targeted improving the quality of results by:

  • trying several different routing topologies to find the best solution,
  • using integrated parasitic extraction to see immediate impact of routing,
  • addressing topology vs. circuit goals,
  • checking for violations against layout specs vs. just DRC rules, and
  • adding DFM treatments to get better yield at smaller process geometries.

The team was able to reduce IP area by removing dedicated routing channels.


They reduced routing time of cell hierarchies from one iteration per month to multiple iterations per week. They removed the need to involve the P&R group for top level cells, cutting days out of their schedules. ECOs were handled natively and cleanly. They had a significant reduction in DRC/LVS issues, and it took less time to fix them.

The design team also used the new router to explore best layout topologies for the move to the next process node. Once they saw that the Pyxis custom router tool made it much easier and faster for their layout engineers, they started using it on IP blocks at advanced technology nodes where the design rules are increasing more complex and found that it is still saving them time and allowing them to produce better designs.

They had a significant reduction in DRC/LVS issues, and it took less time to fix them.”

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