Better Imaging Devices and Better Mixed-Signal Validation with Questa ADMS
In this competitive market, first-time silicon success is critical for meeting time to market. The design team has been providing a video processor that supports cameras up to 8 megapixels at 30 frames per second and an 8 megapixel image sensor. They are constantly striving to provide better services, and as a result AMS verification is mandatory in the current design flow.
Some of the problematic issues they had been dealing with in the past few years were related to bandgap, I/O consumption, interface connectivity and interface timing or video timing on a full frame with different integration time depending on position in frame. They had also to verify the boundary-scan chain path across several power domains, including some analog default registers not set properly, and verify descrambler behavior for color reconstruction.
Their goal was to be able to check the following connectivity between digital and analog blocks during verification:
- Power on reset: Verify behavior with Reset generated internally or externally.
- Check the behavior of I/O buffers during the power-on phase. (The root cause of overconsumption issues was identified with Questa ADMS on a previous design.)
- Measure power consumption in power-down mode.
- Run FirmWare test to verify registers programming.
- Check the functionality on a full frame in different real-life modes.
- Check analog architecture during top-down design exploration.
The team was able to address these issues by first creating a top design using VHDL-AMS models and simulate analog blocks before getting all SPICE block netlists. A “checkerboard” approach to increase simulation speed depending on test sequence allowed us to perform bottom-up verification.
The test plan definition we used identified scenarios for mixed simulations with SPICE models. Our set up of the digital-on-top environment covered:
- Migration from NCSim to Questa ADMS (digital only),
- Integration of VHDL-AMS models,
- Creation of association files to plug SPICE models and automatic power node handling for replacing Verilog
- RTL models by SPICE blocks, and...
- Insertion of automatic converters between analog and digital descriptions.
Next, regressions were run with VHDLAMS models for exhaustive coverage, and we ran a subset of tests with selected SPICE models for accurate validation. Questa ADMS using C++ testbench was available through PLI and test sequence server. Tests were used in both digital and AMS simulation. An example of the validation run is shown in Figure 1, where the sensor image with four sensor cells per “pixel” is descrambled into the final image to create a colored image (each of the four sensor cells having a colored filter RGB). There were no difficulties integrating Questa ADMS with proprietary verification tools for regression testing (automatic test-bench generation).
Results and sensors were functional at first silicon. The IC design team was able to reduce the starting phase between silicon out and first image streaming. They gained better coverage of the functional test sequence obtained for the AMS part of the design. Although devices like these are becoming bigger and more complex, the Questa ADMS methodology is better able to handle the increasing complexity compared with the pure transistor-level simulation. The IC design team was able to meet the goal of a better design and had better coverage for validating the mixed signal part of device using Questa ADMS.
“The IC design team was able to meet the goal of a better design and had better coverage for validating the mixedsignal part of device using Questa ADMS.”