Technical Papers

Mentor Graphics has developed a chip-scale copper electroplating and chemical-mechanical polishing simulator called CMP Optimize. CMP Optimize is part of the Calibre® WORKBench™ platform, and is intended for use with various Design for Manufacturing applications, such as SmartFill optimizations, accurate parasitic extractions, and depth-of-focus variability compensations. CMP Optimize is tightly integrated with Mentor Graphics’ Calibre product line, which provides planarity hotspot detection, as well as thickness analysis and optimization. CMP Optimize is currently the only solution in the industry that gives designers the ability to build models for copper metallization processes. Much like models for lithography, the customer’s process or foundry team builds and owns the copper models. This white paper introduces the CMP Optimize tool from a model-building perspective. It discusses the necessary inputs, model-building methodology from a calibration and optimization standpoint, output data analysis, and model validation capabilities.

This paper documents the results of a critical area and critical feature analysis study of four LSI production 90 nm designs. The recommended rule adherence and statistical sensitivity to random particle defects were evaluated and used to prioritize the yield issues of IP, memories and routing within the various products. Automated correction of recommended rule violations was run in the logic routing to quantify the amount of optimization possible without re-routing the chips. Comparisons were done between the chips to identify commonalities and differences in different design implementations

Fill solutions become more challenging at each smaller node because manufacturing processes and physical interactions become more sensitive to small metal density variations. In addition, the performance of the chip becomes more sensitive to parasitic capacitance (which is increased by adding metal fill) and variations in interconnect resistance (due to CMP impact on metal thickness). Meeting all of these constraints requires better analysis to predict the manufacturing and electrical impacts of fill, and more sophisticated algorithms that optimize the use of metal fill features to solve the three fundamental fill issues. This paper defines the requirements and goals of any fill solution, examines the technology behind Mentor’s four fill solutions, and explains how each can be used to satisfy fill requirements, depending on the needs of the design.

 This paper discusses the features implemented in a Design for Manufacturability (DFM) checker for Critical Feature Analysis of Very Deep Sub-Micron (VDSM) layout designs. This checker leverages Calibre® Yield Analyzer (YA) and Yield Enhancer (YE) functionality, as well as Calibre TCL Verification Format. A central feature of the deck is the identification of opportunities where a layout situation can be improved in a simple, straightforward manner without increasing area inside the top cell boundary. The purpose of such optimization is to increase design robustness to systematic and random yield loss mechanisms and reliability issues without increasing silicon area and cost. An overview of the improvability algorithms implemented using YE features is described, with focus on specific examples of macro code and improvability results on real-life layout cases. Also presented is the use of YA functionality to quantify the gain possible from the application of identified improvements in terms of DFM score. The benefit of this feedback is that it helps designers in prioritizing and selecting the layout improvements to make. Application of the proposed layout optimization flow is finally demonstrated on a 90nm SRAM memory cut design for automotive applications.

We present a new methodology for a balanced yieldoptimization and a new DFM framework which implements it. Our approach allows designers to dynamically balance multiple factors contributing to yield loss and select optimal combination of DFM enhancements based on the current information about the IC layout, the manufacturing process,and known causes of failures. We bring together the information gained from layout analysis, layoutaware circuit analysis, resolution enhancement and optical proximity correction tools, parasitics extraction, timing estimates, and other tools, to suggest the DFM solution which is optimized within the existing constraints on design time and available data. The framework allows us to integrate all available sources of yield information, characterize and compare proposed DFM solutions, quickly adjust them when new data or new analysis tools become available, finetune DFM optimization for a particular design and process and provide the IC designer with a customized solution which characterizes the manufacturability of the design, identifies and classifies areas with the most opportunities for improvement, and suggests DFM improvements. The proposed methodology replaces the adhoc approach to DFM which targets one yield loss cause at a time at the expense of other factors with a comprehensive analysis of competing DFM techniques and tradeoffs between them.

As the advent of advanced process technology such as 65nm and below, the designs become more and more sensitive to the variation of manufacturing process. Though the complicated design rules can guarantee process margin for the most layout environments, some layouts that pass the DRC still have narrow process windows. An effective layout optimization approach based on Litho Friendly Design (LFD), one of Mentor Graphics' products, was introduced to enhance design layout manufacturability. Additional to process window models and production proven Optical Proximity Correction (OPC) recipes, the LFD design kits are also generated and needed, which with the kits and rules people should guarantee no process window issues in a design if the design passes the check of these rules via the kits. Lastly, a real 65nm product Metal layer was applied full chip OPC and post-OPC checks to process variation. Some narrow process window layouts were detected and identified, then optimized for larger process window based on the advices provided by LFD. Both simulation and in-line data showed that the DOFs were improved after the layout optimization without changing the area, timing and power of the original design.