This paper introduces a novel hotspot detection methodology that utilizes pattern matching combined with lithographic simulation. This system will attempt to minimize the negative aspects of both pattern...
In this paper we present a modular approach which combines model based verification, pattern matching and machine learning methods in order to achieve a high accuracy over computing time ratio. We utilize...
Early lithographic hotspot detection has become increasingly important in achieving lithography-friendly designs and manufacturability closure. Fast physical verification tools employing pattern matching...
Among the possible double patterning strategies, self-aligned double patterning (SADP) has moved from Flash-only processes to more general purpose devices. The reason is that while lithoetch-litho-etc (LELE)...
This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon...
TAGS: 3D IC, ATPG, EDT
Presents a verification methodology for 3D-ICs, including connectivity checking and parasitic extraction. Discusses new challenges and EDA tools to responds to those challenges. An example illustrates...
As process technologies advance, a parasitic extraction tool requires more sophisticated extraction capability to obtain the effective sensitivity analysis users need, while still meeting schedules and...
This paper discusses the need to analyze and optimize redundancy schemes for embedded memories in SOC designs with the goal of maximizing yield while minimizing impact on chip area and test. Failure mechanisms,...
TAGS: DO-254
This presentation covers key aspects to the forces from a technology and market perspective that are driving designers towards better energy efficient designs.
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